Diode Tested Devices

DOD400 DAD1 DAD2 DAULED1 DAULED3 DAULED5 DAULED6 DPD101 DPD102 DPD103
DPD104 DPD201 DPD202 DPD501 DPD601 DPD701 DSD1 DSD2 DSD5 DUD21
DUD22 DUD23 DUD24 DUD25 DUD26 DUD31 DUD32 DUD33 DUD34 DUD35
DUD36 DUD4 DUD5 DUD6 DUD7 DUD750 DUD8      

DOD400
Device Loc Side Total Pin Tested Coverage (%) Comment
DOD400 F1 T 6 6 100.0 No Test Nail

Pin Nail Net Name
1 1344 O_KB_DATA_R
2 1 GND
3 1340 O_KB_CLK_R
4 0 NC_1719
5 0 NC_1720
6 0 NC_1721

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1982 DOD400/NP_3_ 0.700V 0.850V 0 D 1340 0 0 1.105V 0.595V NA NA NA NA NA NA  
1983 DOD400/NP_4_ 0.700V 0.850V 0 D 0 0 0 1.105V 0.595V NA NA NA NA NA NA  
1984 DOD400/NP_5_ 0.700V 0.850V 0 D 0 0 0 1.105V 0.595V NA NA NA NA NA NA  
1985 DOD400/NP_6_ 0.700V 0.850V 0 D 1344 0 0 1.105V 0.595V NA NA NA NA NA NA  
1986 DOD400_1_2 0.700V 0.850V 1 D 1 1344 0 1.105V 0.595V 0.870V 0.0003 275.01 253.28 1.1100 0.6000  
1987 DOD400_2_3 0.700V 0.850V 1 D 1 1340 0 1.105V 0.595V 0.870V 0.0002 454.81 423.08 1.1100 0.6000  

DAD1
Device Loc Side Total Pin Tested Coverage (%) Comment
DAD1 A1 T 3 3 100.0  

Pin Nail Net Name
1 12 A_VREF_FMIC1_R
2 13 A_VREF_FMIC1_L
3 14 A_VREF_FMIC1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1926 DAD1_1_2 0.700V 1.500V 0 D 12 13 0 Ignore 1.050V 2.840V 0.0008 178.02 353.18 1.9500 1.0500  
1927 DAD1_2_3 0.396V 0.396V 1 D 14 13 0 0.515V 0.277V 0.400V 0.0003 125.65 122.61 0.5100 0.2800  
1928 DAD1_3_1 0.396V 0.396V 1 D 14 12 0 0.515V 0.277V 0.400V 0.0003 156.13 152.80 0.5100 0.2800  

DAD2
Device Loc Side Total Pin Tested Coverage (%) Comment
DAD2 A1 T 3 3 100.0  

Pin Nail Net Name
1 34 A_VREF_FMIC2_R
2 35 A_VREF_FMIC2_L
3 43 A_VREF_FMIC2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1929 DAD2_1_2 0.700V 1.500V 0 D 34 35 0 Ignore 1.050V 2.840V 0.0009 174.57 346.36 1.9500 1.0500  
1930 DAD2_2_3 0.396V 0.396V 1 D 43 35 0 0.515V 0.277V 0.400V 0.0002 189.67 186.83 0.5100 0.2800  
1931 DAD2_3_1 0.400V 0.400V 1 D 43 34 0 0.520V 0.280V 0.400V 0.0002 221.76 220.30 0.5200 0.2800  

DAULED1
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED1 B1 B 2 2 100.0  

Pin Nail Net Name
1 585 N16978758
2 616 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
4 DAULED1 3.000V 2.000V 1 D 585 616 0 2.600V 1.400V 1.970V 0.0010 196.28 187.87 2.6000 1.4000  

DAULED3
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED3 B1 B 2 2 100.0  

Pin Nail Net Name
1 617 N72387148
2 616 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
5 DAULED3 3.000V 2.000V 1 D 617 616 0 2.600V 1.400V 1.980V 0.0008 249.24 241.62 2.6000 1.4000  

DAULED5
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED5 A1 B 2 2 100.0  

Pin Nail Net Name
1 65 N72387164
2 616 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
6 DAULED5 3.000V 2.000V 1 D 65 616 0 2.600V 1.400V 1.970V 0.0006 324.98 308.80 2.6000 1.4000  

DAULED6
Device Loc Side Total Pin Tested Coverage (%) Comment
DAULED6 B1 B 2 2 100.0  

Pin Nail Net Name
1 602 N72387179
2 616 AULED_GND1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
7 DAULED6 3.000V 2.000V 1 D 602 616 0 2.600V 1.400V 1.980V 0.0010 194.05 186.83 2.6000 1.4000  

DPD101
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD101 F2 T 3 3 100.0 D

Pin Nail Net Name
1 405 +5VSB
2 1339 +12V_CPU
3 1333 P_DRIVER1_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1988 DPD101_1_2/D 0.700V 1.500V 0 D 405 1339 0 Ignore 1.050V NA NA NA NA NA NA  
1989 DPD101_2_3 0.415V 0.415V 1 D 1339 1333 0 0.539V 0.290V 0.410V 0.0003 164.29 152.49 0.5400 0.2900  
1990 DPD101_3_1 0.419V 0.419V 1 D 405 1333 0 0.545V 0.293V 0.400V 0.0006 69.141 60.257 0.5400 0.2900  

DPD102
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD102 E2 T 3 3 100.0 D

Pin Nail Net Name
1 405 +5VSB
2 1339 +12V_CPU
3 1038 P_DRIVER2_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1991 DPD102_1_2/D 0.700V 1.500V 0 D 405 1339 0 Ignore 1.050V NA NA NA NA NA NA  
1992 DPD102_2_3 0.414V 0.414V 1 D 1339 1038 0 0.538V 0.290V 0.400V 0.0003 136.74 121.64 0.5400 0.2900  
1993 DPD102_3_1 0.418V 0.418V 1 D 405 1038 0 0.543V 0.293V 0.400V 0.0007 56.040 49.321 0.5400 0.2900  

DPD103
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD103 E2 T 3 3 100.0 D

Pin Nail Net Name
1 405 +5VSB
2 1339 +12V_CPU
3 1032 P_DRIVER3_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1994 DPD103_1_2/D 0.700V 1.500V 0 D 405 1339 0 Ignore 1.050V NA NA NA NA NA NA  
1995 DPD103_2_3 0.416V 0.416V 1 D 1339 1032 0 0.541V 0.291V 0.400V 0.0002 238.69 209.85 0.5400 0.2900  
1996 DPD103_3_1 0.420V 0.420V 1 D 405 1032 0 0.546V 0.294V 0.400V 0.0003 129.00 113.58 0.5500 0.2900  

DPD104
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD104 E2 T 3 3 100.0 D

Pin Nail Net Name
1 405 +5VSB
2 1339 +12V_CPU
3 1031 P_DRIVER4_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1997 DPD104_1_2/D 0.700V 1.500V 0 D 405 1339 0 Ignore 1.050V NA NA NA NA NA NA  
1998 DPD104_2_3 0.415V 0.415V 1 D 1339 1031 0 0.539V 0.290V 0.400V 0.0005 79.755 70.637 0.5400 0.2900  
1999 DPD104_3_1 0.419V 0.419V 1 D 405 1031 0 0.545V 0.293V 0.410V 0.0011 39.361 34.982 0.5400 0.2900  

DPD201
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD201 F3 T 3 3 100.0 D

Pin Nail Net Name
1 405 +5VSB
2 1339 +12V_CPU
3 1299 P_GT_DRIVER_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2000 DPD201_1_2/D 0.700V 1.500V 0 D 405 1339 0 Ignore 1.050V NA NA NA NA NA NA  
2001 DPD201_2_3 0.417V 0.417V 1 D 1339 1299 0 0.542V 0.292V 0.400V 0.0009 47.954 41.807 0.5400 0.2900  
2002 DPD201_3_1 0.422V 0.422V 1 D 405 1299 0 0.549V 0.295V 0.410V 0.0008 53.058 46.596 0.5500 0.3000  

DPD202
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD202 F3 T 3 3 100.0 D

Pin Nail Net Name
1 405 +5VSB
2 1339 +12V_CPU
3 1303 P_GT_DRIVER2_VCC_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2003 DPD202_1_2/D 0.700V 1.500V 0 D 405 1339 0 Ignore 1.050V NA NA NA NA NA NA  
2004 DPD202_2_3 0.417V 0.417V 1 D 1339 1303 0 0.542V 0.292V 0.400V 0.0005 89.063 78.311 0.5400 0.2900  
2005 DPD202_3_1 0.422V 0.422V 1 D 405 1303 0 0.549V 0.295V 0.410V 0.0006 74.978 65.835 0.5500 0.3000  

DPD501
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD501 F4 T 3 3 100.0 C

Pin Nail Net Name
1 1178 +5VDUAL
2 4 +12V
3 1183 P_VDDQ_VCC_P_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2006 DPD501_1_2/C 0.700V 1.500V 0 D 1178 4 0 Ignore 1.050V NA NA NA NA NA NA  
2007 DPD501_2_3 0.411V 0.411V 1 D 4 1183 0 0.534V 0.288V 0.390V 0.0005 82.933 70.840 0.5300 0.2900  
2008 DPD501_3_1 0.415V 0.415V 1 D 1178 1183 0 0.539V 0.290V 0.390V 0.0005 77.113 59.065 0.5400 0.2900  

DPD601
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD601 B4 T 3 3 100.0 No Test Nail

Pin Nail Net Name
1 0 NC_1824
2 381 P_5VSB_GATE_D_10
3 377 P_5VSB_GATE_10_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2009 DPD601/NP_1_ 0.700V 0.700V 0 D 0 381 0 0.910V 0.490V NA NA NA NA NA NA  
2010 DPD601/NP_3_ 0.700V 0.700V 0 D 0 377 0 0.910V 0.490V NA NA NA NA NA NA  
2011 DPD601_2_3 0.408V 0.408V 1 D 377 381 0 0.530V 0.286V 0.410V 0.0002 202.08 199.10 0.5300 0.2900  

DPD701
Device Loc Side Total Pin Tested Coverage (%) Comment
DPD701 B4 T 3 3 100.0  

Pin Nail Net Name
1 404 N15799000
2 403 P_+1_0V_A_PG_10
3 130 O_RSMRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2012 DPD701_1_2 0.700V 1.500V 0 D 404 403 0 Ignore 1.050V 2.840V 0.0007 225.60 447.86 1.9500 1.0500  
2013 DPD701_2_3 0.416V 0.416V 1 D 130 403 0 0.541V 0.291V 0.420V 0.0004 102.55 100.53 0.5400 0.2900  
2014 DPD701_3_1 0.416V 0.416V 1 D 130 404 0 0.541V 0.291V 0.420V 0.0003 121.38 119.19 0.5400 0.2900  

DSD1
Device Loc Side Total Pin Tested Coverage (%) Comment
DSD1 C2 T 3 3 100.0  

Pin Nail Net Name
1 680 N74741034
2 681 +BAT_R
3 71 +3V_BAT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2015 DSD1_1_2 0.700V 1.500V 0 D 680 681 0 Ignore 1.050V 2.840V 0.0004 372.16 738.91 1.9500 1.0500  
2016 DSD1_2_3 0.416V 0.416V 1 D 681 71 0 0.541V 0.291V 0.420V 0.0002 176.82 173.64 0.5400 0.2900  
2017 DSD1_3_1 0.416V 0.416V 1 D 680 71 0 0.541V 0.291V 0.420V 0.0002 225.50 222.28 0.5400 0.2900  

DSD2
Device Loc Side Total Pin Tested Coverage (%) Comment
DSD2 C2 T 3 3 100.0  

Pin Nail Net Name
1 673 N45021399
2 941 H_THERMTRIP_
3 494 S_VCORE_SHDN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2018 DSD2_1_2 0.700V 1.500V 0 D 673 941 0 Ignore 1.050V 2.840V 0.0007 214.99 425.71 1.9500 1.0500  
2019 DSD2_2_3 0.407V 0.407V 1 D 494 941 0 0.529V 0.285V 0.410V 0.0004 103.46 101.17 0.5300 0.2800  
2020 DSD2_3_1 0.405V 0.405V 1 D 494 673 0 0.527V 0.284V 0.410V 0.0005 87.124 84.923 0.5300 0.2800  

DSD5
Device Loc Side Total Pin Tested Coverage (%) Comment
DSD5 A4 T 3 3 100.0 No Test Nail

Pin Nail Net Name
1 427 S_SLP_S3_
2 0 NC_1825
3 136 S_SYSPWROK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2024 DSD5/NP_1_2 0.700V 0.700V 0 D 427 0 0 0.910V 0.490V NA NA NA NA NA NA  
2025 DSD5/NP_2_3 0.700V 0.700V 0 D 0 136 0 0.910V 0.490V NA NA NA NA NA NA  
2026 DSD5_3_1 0.443V 0.443V 1 D 136 427 0 0.576V 0.310V 0.450V 0.0008 58.844 57.108 0.5800 0.3100  

DUD21
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD21 A2 T 6 6 100.0  

Pin Nail Net Name
1 170 S_U2DP1
2 1 GND
3 176 S_U2DP2
4 175 S_U2DN2
5 405 +5VSB
6 171 S_U2DN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2027 DUD21_1_2 0.700V 0.850V 1 D 1 170 0 1.105V 0.595V 0.810V 0.0001 584.62 496.00 1.1100 0.6000  
2028 DUD21_2_3 0.700V 0.850V 1 D 1 176 0 1.105V 0.595V 0.820V 0.0002 446.99 386.64 1.1100 0.6000  
2029 DUD21_3_4 0.700V 0.850V 1 D 1 175 0 1.105V 0.595V 0.820V 0.0002 541.28 473.31 1.1100 0.6000  
2030 DUD21_4_5 0.700V 0.850V 1 D 175 405 0 1.105V 0.595V 0.870V 0.0001 619.14 562.08 1.1100 0.6000  
2031 DUD21_5_6 0.700V 0.850V 1 D 171 405 0 1.105V 0.595V 0.870V 0.0001 748.62 677.36 1.1100 0.6000  
2032 DUD21_6_1 0.700V 0.850V 1 D 170 405 0 1.105V 0.595V 0.870V 0.0002 417.01 376.39 1.1100 0.6000  

DUD22
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD22 D1 T 6 6 100.0  

Pin Nail Net Name
1 975 S_U2DP3
2 1 GND
3 994 S_U2DP4
4 995 S_U2DN4
5 405 +5VSB
6 974 S_U2DN3

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2033 DUD22_1_2 0.700V 0.850V 1 D 1 975 0 1.105V 0.595V 0.820V 0.0002 343.08 303.35 1.1100 0.6000  
2034 DUD22_2_3 0.700V 0.850V 1 D 1 994 0 1.105V 0.595V 0.820V 0.0003 281.95 251.11 1.1100 0.6000  
2035 DUD22_3_4 0.700V 0.850V 1 D 1 995 0 1.105V 0.595V 0.820V 0.0003 267.83 239.64 1.1100 0.6000  
2036 DUD22_4_5 0.700V 0.850V 1 D 995 405 0 1.105V 0.595V 0.870V 0.0003 330.68 302.32 1.1100 0.6000  
2037 DUD22_5_6 0.700V 0.850V 1 D 974 405 0 1.105V 0.595V 0.870V 0.0002 452.58 413.42 1.1100 0.6000  
2038 DUD22_6_1 0.700V 0.850V 1 D 975 405 0 1.105V 0.595V 0.870V 0.0002 375.84 342.97 1.1100 0.6000  

DUD23
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD23 D1 T 6 6 100.0  

Pin Nail Net Name
1 981 S_U2DP5
2 1 GND
3 986 S_U2DP6
4 987 S_U2DN6
5 405 +5VSB
6 980 S_U2DN5

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2039 DUD23_1_2 0.700V 0.850V 1 D 1 981 0 1.105V 0.595V 0.820V 0.0002 404.31 360.75 1.1100 0.6000  
2040 DUD23_2_3 0.700V 0.850V 1 D 1 986 0 1.105V 0.595V 0.820V 0.0002 346.72 311.29 1.1100 0.6000  
2041 DUD23_3_4 0.700V 0.850V 1 D 1 987 0 1.105V 0.595V 0.820V 0.0002 372.75 335.17 1.1100 0.6000  
2042 DUD23_4_5 0.700V 0.850V 1 D 987 405 0 1.105V 0.595V 0.870V 0.0001 595.48 543.25 1.1100 0.6000  
2043 DUD23_5_6 0.700V 0.850V 1 D 980 405 0 1.105V 0.595V 0.870V 0.0001 588.01 535.36 1.1100 0.6000  
2044 DUD23_6_1 0.700V 0.850V 1 D 981 405 0 1.105V 0.595V 0.870V 0.0003 336.15 306.85 1.1100 0.6000  

DUD24
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD24 A2 T 6 6 100.0  

Pin Nail Net Name
1 170 S_U2DP1
2 1 GND
3 176 S_U2DP2
4 175 S_U2DN2
5 405 +5VSB
6 171 S_U2DN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2045 DUD24_1_2 0.700V 0.850V 1 D 1 170 0 1.105V 0.595V 0.820V 0.0003 288.37 257.66 1.1100 0.6000  
2046 DUD24_2_3 0.700V 0.850V 1 D 1 176 0 1.105V 0.595V 0.820V 0.0003 338.82 305.04 1.1100 0.6000  
2047 DUD24_3_4 0.700V 0.850V 1 D 1 175 0 1.105V 0.595V 0.820V 0.0003 304.92 274.21 1.1100 0.6000  
2048 DUD24_4_5 0.700V 0.850V 1 D 175 405 0 1.105V 0.595V 0.870V 0.0002 564.44 510.30 1.1100 0.6000  
2049 DUD24_5_6 0.700V 0.850V 1 D 171 405 0 1.105V 0.595V 0.870V 0.0002 505.50 457.05 1.1100 0.6000  
2050 DUD24_6_1 0.700V 0.850V 1 D 170 405 0 1.105V 0.595V 0.870V 0.0002 372.41 336.18 1.1100 0.6000  

DUD25
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD25 D1 T 6 6 100.0  

Pin Nail Net Name
1 994 S_U2DP4
2 1 GND
3 975 S_U2DP3
4 974 S_U2DN3
5 405 +5VSB
6 995 S_U2DN4

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2051 DUD25_1_2 0.700V 0.850V 1 D 1 994 0 1.105V 0.595V 0.820V 0.0003 255.46 227.79 1.1100 0.6000  
2052 DUD25_2_3 0.700V 0.850V 1 D 1 975 0 1.105V 0.595V 0.820V 0.0002 342.00 306.22 1.1100 0.6000  
2053 DUD25_3_4 0.700V 0.850V 1 D 1 974 0 1.105V 0.595V 0.820V 0.0002 354.89 318.56 1.1100 0.6000  
2054 DUD25_4_5 0.700V 0.850V 1 D 974 405 0 1.105V 0.595V 0.870V 0.0001 693.54 634.15 1.1100 0.6000  
2055 DUD25_5_6 0.700V 0.850V 1 D 995 405 0 1.105V 0.595V 0.870V 0.0002 503.70 459.53 1.1100 0.6000  
2056 DUD25_6_1 0.700V 0.850V 1 D 994 405 0 1.105V 0.595V 0.870V 0.0002 433.71 395.99 1.1100 0.6000  

DUD26
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD26 D1 T 6 6 100.0  

Pin Nail Net Name
1 986 S_U2DP6
2 1 GND
3 981 S_U2DP5
4 980 S_U2DN5
5 405 +5VSB
6 987 S_U2DN6

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2057 DUD26_1_2 0.700V 0.850V 1 D 1 986 0 1.105V 0.595V 0.820V 0.0002 349.23 312.76 1.1100 0.6000  
2058 DUD26_2_3 0.700V 0.850V 1 D 1 981 0 1.105V 0.595V 0.820V 0.0003 282.56 253.33 1.1100 0.6000  
2059 DUD26_3_4 0.700V 0.850V 1 D 1 980 0 1.105V 0.595V 0.820V 0.0003 286.71 258.16 1.1100 0.6000  
2060 DUD26_4_5 0.700V 0.850V 1 D 980 405 0 1.105V 0.595V 0.870V 0.0002 443.56 404.38 1.1100 0.6000  
2061 DUD26_5_6 0.700V 0.850V 1 D 987 405 0 1.105V 0.595V 0.870V 0.0002 413.94 377.01 1.1100 0.6000  
2062 DUD26_6_1 0.700V 0.850V 1 D 986 405 0 1.105V 0.595V 0.870V 0.0003 313.41 285.13 1.1100 0.6000  

DUD31
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD31 A2 T 9 9 100.0  

Pin Nail Net Name
1 124 S_U3RXDP1
2 123 S_U3RXDN1
3 1 GND
4 126 S_U3RXDP2
5 125 S_U3RXDN2
6 125 S_U3RXDN2
7 126 S_U3RXDP2
8 123 S_U3RXDN1
9 124 S_U3RXDP1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2063 DUD31_1_2 0.700V 0.850V 1 D 1 124 0 1.105V 0.595V 0.850V 0.0003 280.82 276.36 1.1100 0.6000  
2064 DUD31_2_3 0.700V 0.850V 1 D 1 123 0 1.105V 0.595V 0.860V 0.0003 286.61 280.20 1.1100 0.6000  
2065 DUD31_3_4 0.700V 0.850V 1 D 1 126 0 1.105V 0.595V 0.860V 0.0003 267.17 260.92 1.1100 0.6000  
2066 DUD31_4_5 0.700V 0.850V 1 D 1 125 0 1.105V 0.595V 0.860V 0.0002 449.98 437.59 1.1100 0.6000  

DUD32
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD32 A2 T 9 9 100.0  

Pin Nail Net Name
1 127 S_U3TXDN1
2 172 S_U3TXDP1
3 1 GND
4 173 S_U3TXDN2
5 174 S_U3TXDP2
6 174 S_U3TXDP2
7 173 S_U3TXDN2
8 172 S_U3TXDP1
9 127 S_U3TXDN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2067 DUD32_1_2 0.700V 0.850V 1 D 1 127 0 1.105V 0.595V 0.900V 0.0002 453.30 363.35 1.1100 0.6000  
2068 DUD32_2_3 0.700V 0.850V 1 D 1 172 0 1.105V 0.595V 0.900V 0.0002 456.82 365.15 1.1100 0.6000  
2069 DUD32_3_4 0.700V 0.850V 1 D 1 173 0 1.105V 0.595V 0.900V 0.0002 444.90 354.56 1.1100 0.6000  
2070 DUD32_4_5 0.700V 0.850V 1 D 1 174 0 1.105V 0.595V 0.900V 0.0002 480.94 386.37 1.1100 0.6000  

DUD33
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD33 D1 T 9 9 100.0  

Pin Nail Net Name
1 996 S_U3TXDN4
2 997 S_U3TXDP4
3 1 GND
4 973 S_U3TXDN3
5 972 S_U3TXDP3
6 972 S_U3TXDP3
7 973 S_U3TXDN3
8 997 S_U3TXDP4
9 996 S_U3TXDN4

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2071 DUD33_1_2 0.700V 0.850V 1 D 1 996 0 1.105V 0.595V 0.900V 0.0002 350.73 285.00 1.1100 0.6000  
2072 DUD33_2_3 0.700V 0.850V 1 D 1 997 0 1.105V 0.595V 0.900V 0.0002 405.24 328.30 1.1100 0.6000  
2073 DUD33_3_4 0.700V 0.850V 1 D 1 973 0 1.105V 0.595V 0.900V 0.0002 435.38 351.76 1.1100 0.6000  
2074 DUD33_4_5 0.700V 0.850V 1 D 1 972 0 1.105V 0.595V 0.900V 0.0002 384.73 313.99 1.1100 0.6000  

DUD34
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD34 D1 T 9 9 100.0  

Pin Nail Net Name
1 977 S_U3RXDN3
2 976 S_U3RXDP3
3 1 GND
4 992 S_U3RXDN4
5 993 S_U3RXDP4
6 993 S_U3RXDP4
7 992 S_U3RXDN4
8 976 S_U3RXDP3
9 977 S_U3RXDN3

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2075 DUD34_1_2 0.700V 0.850V 1 D 1 977 0 1.105V 0.595V 0.850V 0.0003 321.94 317.23 1.1100 0.6000  
2076 DUD34_2_3 0.700V 0.850V 1 D 1 976 0 1.105V 0.595V 0.850V 0.0003 290.16 284.63 1.1100 0.6000  
2077 DUD34_3_4 0.700V 0.850V 1 D 1 992 0 1.105V 0.595V 0.850V 0.0002 413.56 406.26 1.1100 0.6000  
2078 DUD34_4_5 0.700V 0.850V 1 D 1 993 0 1.105V 0.595V 0.850V 0.0003 330.66 326.81 1.1100 0.6000  

DUD35
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD35 D1 T 9 9 100.0  

Pin Nail Net Name
1 983 S_U3RXDN5
2 982 S_U3RXDP5
3 1 GND
4 984 S_U3RXDN6
5 985 S_U3RXDP6
6 985 S_U3RXDP6
7 984 S_U3RXDN6
8 982 S_U3RXDP5
9 983 S_U3RXDN5

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2079 DUD35_1_2 0.700V 0.850V 1 D 1 983 0 1.105V 0.595V 0.850V 0.0002 370.83 365.71 1.1100 0.6000  
2080 DUD35_2_3 0.700V 0.850V 1 D 1 982 0 1.105V 0.595V 0.850V 0.0002 401.48 394.17 1.1100 0.6000  
2081 DUD35_3_4 0.700V 0.850V 1 D 1 984 0 1.105V 0.595V 0.850V 0.0002 358.00 351.71 1.1100 0.6000  
2082 DUD35_4_5 0.700V 0.850V 1 D 1 985 0 1.105V 0.595V 0.850V 0.0003 327.05 322.80 1.1100 0.6000  

DUD36
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD36 D1 T 9 9 100.0  

Pin Nail Net Name
1 979 S_U3TXDN5
2 978 S_U3TXDP5
3 1 GND
4 988 S_U3TXDN6
5 989 S_U3TXDP6
6 989 S_U3TXDP6
7 988 S_U3TXDN6
8 978 S_U3TXDP5
9 979 S_U3TXDN5

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2083 DUD36_1_2 0.700V 0.850V 1 D 1 979 0 1.105V 0.595V 0.900V 0.0002 378.64 307.25 1.1100 0.6000  
2084 DUD36_2_3 0.700V 0.850V 1 D 1 978 0 1.105V 0.595V 0.900V 0.0002 414.26 332.67 1.1100 0.6000  
2085 DUD36_3_4 0.700V 0.850V 1 D 1 988 0 1.105V 0.595V 0.900V 0.0002 454.64 367.12 1.1100 0.6000  
2086 DUD36_4_5 0.700V 0.850V 1 D 1 989 0 1.105V 0.595V 0.900V 0.0002 448.47 364.22 1.1100 0.6000  

DUD4
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD4 C1 T 6 6 100.0  

Pin Nail Net Name
1 626 S_USB_PP6
2 1 GND
3 622 S_USB_PP7
4 623 S_USB_PN7
5 405 +5VSB
6 625 S_USB_PN6

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2087 DUD4_1_2 0.700V 0.850V 1 D 1 626 0 1.105V 0.595V 0.830V 0.0002 361.23 338.51 1.1100 0.6000  
2088 DUD4_2_3 0.700V 0.850V 1 D 1 622 0 1.105V 0.595V 0.830V 0.0003 299.77 280.96 1.1100 0.6000  
2089 DUD4_3_4 0.700V 0.850V 1 D 1 623 0 1.105V 0.595V 0.830V 0.0003 296.69 277.88 1.1100 0.6000  
2090 DUD4_4_5 0.700V 0.850V 1 D 623 405 0 1.105V 0.595V 0.910V 0.0003 290.63 223.85 1.1100 0.6000  
2091 DUD4_5_6 0.700V 0.850V 1 D 625 405 0 1.105V 0.595V 0.910V 0.0003 334.13 257.81 1.1100 0.6000  
2092 DUD4_6_1 0.700V 0.850V 1 D 626 405 0 1.105V 0.595V 0.910V 0.0002 357.74 275.30 1.1100 0.6000  

DUD5
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD5 F1 T 6 6 100.0  

Pin Nail Net Name
1 1345 S_USB_PP8
2 1 GND
3 1349 S_USB_PP9
4 1348 S_USB_PN9
5 405 +5VSB
6 1346 S_USB_PN8

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2093 DUD5_1_2 0.700V 0.850V 1 D 1 1345 0 1.105V 0.595V 0.830V 0.0005 164.86 152.53 1.1100 0.6000  
2094 DUD5_2_3 0.700V 0.850V 1 D 1 1349 0 1.105V 0.595V 0.830V 0.0002 352.68 331.55 1.1100 0.6000  
2095 DUD5_3_4 0.700V 0.850V 1 D 1 1348 0 1.105V 0.595V 0.870V 0.0210 4.0430 3.7630 1.1100 0.6000  
2096 DUD5_4_5 0.700V 0.850V 1 D 1348 405 0 1.105V 0.595V 0.920V 0.0206 4.1250 3.0570 1.1100 0.6000  
2097 DUD5_5_6 0.700V 0.850V 1 D 1346 405 0 1.105V 0.595V 0.880V 0.0005 157.32 139.61 1.1100 0.6000  
2098 DUD5_6_1 0.700V 0.850V 1 D 1345 405 0 1.105V 0.595V 0.880V 0.0004 191.56 167.78 1.1100 0.6000  

DUD6
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD6 A2 T 6 6 100.0  

Pin Nail Net Name
1 112 S_USB_PP10
2 1 GND
3 111 S_USB_PP11
4 110 S_USB_PN11
5 405 +5VSB
6 108 S_USB_PN10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2099 DUD6_1_2 0.700V 0.850V 1 D 1 112 0 1.105V 0.595V 0.820V 0.0003 313.16 278.99 1.1100 0.6000  
2100 DUD6_2_3 0.700V 0.850V 1 D 1 111 0 1.105V 0.595V 0.820V 0.0003 306.38 274.29 1.1100 0.6000  
2101 DUD6_3_4 0.700V 0.850V 1 D 1 110 0 1.105V 0.595V 0.820V 0.0003 279.75 250.69 1.1100 0.6000  
2102 DUD6_4_5 0.700V 0.850V 1 D 110 405 0 1.105V 0.595V 0.870V 0.0002 481.53 438.89 1.1100 0.6000  
2103 DUD6_5_6 0.700V 0.850V 1 D 108 405 0 1.105V 0.595V 0.870V 0.0001 688.23 625.05 1.1100 0.6000  
2104 DUD6_6_1 0.700V 0.850V 1 D 112 405 0 1.105V 0.595V 0.870V 0.0002 406.04 369.09 1.1100 0.6000  

DUD7
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD7 F1 T 6 6 100.0  

Pin Nail Net Name
1 1345 S_USB_PP8
2 1 GND
3 1349 S_USB_PP9
4 1348 S_USB_PN9
5 405 +5VSB
6 1346 S_USB_PN8

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2108 DUD7_1_2 0.700V 0.850V 1 D 1 1345 0 1.105V 0.595V 0.830V 0.0005 158.83 146.83 1.1100 0.6000  
2109 DUD7_2_3 0.700V 0.850V 1 D 1 1349 0 1.105V 0.595V 0.830V 0.0004 233.85 219.80 1.1100 0.6000  
2110 DUD7_3_4 0.700V 0.850V 1 D 1 1348 0 1.105V 0.595V 0.870V 0.0211 4.0360 3.7560 1.1100 0.6000  
2111 DUD7_4_5 0.700V 0.850V 1 D 1348 405 0 1.105V 0.595V 0.920V 0.0207 4.1090 3.0460 1.1100 0.6000  
2112 DUD7_5_6 0.700V 0.850V 1 D 1346 405 0 1.105V 0.595V 0.880V 0.0006 151.56 134.50 1.1100 0.6000  
2113 DUD7_6_1 0.700V 0.850V 1 D 1345 405 0 1.105V 0.595V 0.880V 0.0005 157.93 138.38 1.1100 0.6000  

DUD750
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD750 B4 T 3 3 100.0 No Test Nail

Pin Nail Net Name
1 0 NC_1823
2 373 N75707997
3 376 P_5VSB_USB_GATE_10_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2105 DUD750/NP_1_ 0.700V 0.700V 0 D 0 373 0 0.910V 0.490V NA NA NA NA NA NA  
2106 DUD750/NP_3_ 0.700V 0.700V 0 D 0 376 0 0.910V 0.490V NA NA NA NA NA NA  
2107 DUD750_2_3 0.406V 0.406V 1 D 376 373 0 0.528V 0.284V 0.410V 0.0002 216.88 212.74 0.5300 0.2800  

DUD8
Device Loc Side Total Pin Tested Coverage (%) Comment
DUD8 A2 T 6 6 100.0  

Pin Nail Net Name
1 112 S_USB_PP10
2 1 GND
3 111 S_USB_PP11
4 110 S_USB_PN11
5 405 +5VSB
6 108 S_USB_PN10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
2114 DUD8_1_2 0.700V 0.850V 1 D 1 112 0 1.105V 0.595V 0.820V 0.0004 233.82 208.21 1.1100 0.6000  
2115 DUD8_2_3 0.700V 0.850V 1 D 1 111 0 1.105V 0.595V 0.820V 0.0003 311.09 278.51 1.1100 0.6000  
2116 DUD8_3_4 0.700V 0.850V 1 D 1 110 0 1.105V 0.595V 0.820V 0.0003 332.78 298.51 1.1100 0.6000  
2117 DUD8_4_5 0.700V 0.850V 1 D 110 405 0 1.105V 0.595V 0.870V 0.0002 380.67 346.80 1.1100 0.6000  
2118 DUD8_5_6 0.700V 0.850V 1 D 108 405 0 1.105V 0.595V 0.870V 0.0002 457.41 415.34 1.1100 0.6000  
2119 DUD8_6_1 0.700V 0.850V 1 D 112 405 0 1.105V 0.595V 0.870V 0.0002 454.10 412.84 1.1100 0.6000