Capacitor Tested Devices

CBC1 CBC2 CBC3 CBC4 CBC5 CBC6 CBC7 CBC8 CEC30 CL1C90
CL1C91 CL1C92 CL1C93 CL1U1C22 CD3C366 CD3C46 CD3C47 CD3C48 CPC101 CPC102
CPC103 CPC104 CPC105 CPC106 CPC107 CPC108 CPC109 CPC110 CPC115 CPC116
CPC118 CPC121 CPC122 CPC123 CPC124 CPC126 CPC128 CPC132 CPC133 CPC137
CPC138 CPC139 CPC140 CPC141 CPC142 CPC143 CPC144 CPC145 CPC193 CPC194
CPC199 CPC201 CPC202 CPC203 CPC204 CPC412 CPC414 CPC415 CPC418 CPC419
CPC530 CPC531 CPC532 CPC536 CPC537 CPC539 CPC549 CPC552 CPC605 CPC606
CPC607 CPC613 CPC630 CPC701 CPC715 CPC731 CPC732 CPC736 CPC740 CPC751
CPC752 CPC757 CPC759 CPC760 CPC803 CPC804 CPC807 CAC1 CAC13 CAC14
CAC17 CAC18 CAC19 CAC2 CAC20 CAC21 CAC22 CAC24 CAC251 CAC252
CAC27 CAC3 CAC37 CAC38 CAC4 CAC5 CAC6 CACE1 CACE10 CACE2
CACE9 CAU1C238 CAU1C27 CAU1C3 CAU2C4 CESDC14 CESDC5 CESDC7 CESDC8 CESDC9
CESDO1C15 CESDO1C3 CESDOC205 CHC24 CHTC1 CO1C12 CO1C32 CO1C34 COC1 COC2
COC202 COC206 COC301 COC311 COC760 COC761 COTC1 COU1C31 COU1C45 COU1C53
CPCE103 CPCE109 CPCE207 CPCE516 CPCE518 CPCE707 CSC3 CSC59 CSC60 CUC750
CUCE1 CXCE1                

CBC1
Device Loc Side Total Pin Tested Coverage (%) Comment
CBC1 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 667 LS_COM1_RXD1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1519 CBC1 150.00pF 150.00pF 2 C 1 667 0 240.00pF 90.00pF 151.66pF 3.8897 6.4270 5.2840 240.00 90.000  

CBC2
Device Loc Side Total Pin Tested Coverage (%) Comment
CBC2 C2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 661 LS_COM1_TXD1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1520 CBC2 150.00pF 150.00pF 2 C 1 661 0 240.00pF 90.00pF 150.02pF 0.0806 310.27 248.30 240.00 90.000  

CBC3
Device Loc Side Total Pin Tested Coverage (%) Comment
CBC3 C2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 663 LS_COM1_RI1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1521 CBC3 150.00pF 150.00pF 2 C 1 663 0 240.00pF 90.00pF 159.05pF 5.4198 4.6130 4.2470 240.00 90.000  

CBC4
Device Loc Side Total Pin Tested Coverage (%) Comment
CBC4 C2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 666 LS_COM1_DTR1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1522 CBC4 150.00pF 150.00pF 2 C 1 666 0 240.00pF 90.00pF 150.06pF 0.1035 241.45 193.36 240.00 90.000  

CBC5
Device Loc Side Total Pin Tested Coverage (%) Comment
CBC5 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 660 LS_COM1_DCD1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1523 CBC5 150.00pF 150.00pF 2 C 1 660 0 240.00pF 90.00pF 152.41pF 2.3361 10.702 8.9050 240.00 90.000  

CBC6
Device Loc Side Total Pin Tested Coverage (%) Comment
CBC6 C2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 664 LS_COM1_CTS1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1524 CBC6 150.00pF 150.00pF 2 C 1 664 0 240.00pF 90.00pF 152.70pF 4.4500 5.6180 4.6960 240.00 90.000  

CBC7
Device Loc Side Total Pin Tested Coverage (%) Comment
CBC7 C2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 662 LS_COM1_RTS1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1525 CBC7 150.00pF 150.00pF 2 C 1 662 0 240.00pF 90.00pF 150.08pF 0.0568 440.02 352.47 240.00 90.000  

CBC8
Device Loc Side Total Pin Tested Coverage (%) Comment
CBC8 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 665 LS_COM1_DSR1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1526 CBC8 150.00pF 150.00pF 2 C 1 665 0 240.00pF 90.00pF 147.83pF 4.1553 6.0160 4.6390 240.00 90.000  

CEC30
Device Loc Side Total Pin Tested Coverage (%) Comment
CEC30 A3 T 2 2 100.0  

Pin Nail Net Name
1 169 S_PLTRST__R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1551 CEC30 1000.0pF 1000.0pF 1 C 1 169 0 1600.0pF 600.0pF 1000.5pF 2.9781 55.963 44.824 1600.0 600.00  

CL1C90
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1C90 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 641 L1_ACTLEDP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1552 CL1C90 1000.0pF 1000.0pF 2 C 1 641 651 1600.0pF 600.0pF 1038.3pF 17.881 9.3210 8.1700 1600.0 600.00  

CL1C91
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1C91 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 640 L1_ACTLEDN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1553 CL1C91 1000.0pF 1000.0pF 2 C 1 640 0 1600.0pF 600.0pF 1118.4pF 1.6043 103.89 100.06 1600.0 600.00  

CL1C92
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1C92 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 639 L1_LINK1000_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1554 CL1C92 1000.0pF 1000.0pF 0 C 1 639 0 1600.0pF 600.0pF 1277.3pF 2.3633 70.522 45.511 1600.0 600.00  

CL1C93
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1C93 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 638 L1_LINK100_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1555 CL1C93 1000.0pF 1000.0pF 0 C 1 638 0 1600.0pF 600.0pF 1149.1pF 0.8055 206.91 186.58 1600.0 600.00  

CL1U1C22
Device Loc Side Total Pin Tested Coverage (%) Comment
CL1U1C22 B1 T 2 2 100.0 Parallel CL1U1C3

Pin Nail Net Name
1 646 +L1_1_0V
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1766 CL1U1C22/CL1U 1.000uF 1.400uF 0 C 1 646 0 2.240uF 0.840uF 1.310uF 0.0010 241.23 162.73 2.2400 0.8400  

CD3C366
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C366 F4 T 2 2 100.0 Parallel CD3C5

Pin Nail Net Name
1 1193 H_D3B_VREFDQ
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1788 CD3C366/CD3C5 4.700uF 11.40uF 4 C 1 1193 0 18.24uF 6.84uF 10.80uF 0.0580 32.747 22.730 18.240 6.8400  

CD3C46
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C46 F4 T 2 2 100.0  

Pin Nail Net Name
1 1218 H_D3A_VREFDQ_R
2 1221 N60799296

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1594 CD3C46 0.0220uF 0.0220uF 1 C 1218 1221 1 0.0352uF 0.0132uF 0.0300uF 0.0001 29.847 23.802 0.0400 0.0100  

CD3C47
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C47 F4 T 2 2 100.0  

Pin Nail Net Name
1 1219 H_D3B_VREFDQ_R
2 1203 N60799295

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1595 CD3C47 0.0220uF 0.0220uF 2 C 1219 1203 1 0.0352uF 0.0132uF 0.0200uF 0.0000 89.672 88.007 0.0400 0.0100  

CD3C48
Device Loc Side Total Pin Tested Coverage (%) Comment
CD3C48 D4 T 2 2 100.0  

Pin Nail Net Name
1 1202 H_D3_VREFCA
2 798 N60799305

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1596 CD3C48 0.0220uF 0.0220uF 2 C 1202 798 1 0.0352uF 0.0132uF 0.0200uF 0.0001 37.814 27.801 0.0400 0.0100  

CPC101
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC101 F3 T 2 2 100.0  

Pin Nail Net Name
1 1244 P_GT_FBA_10
2 1242 P_GT_DIFFA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1531 CPC101 330.00pF 330.00pF 2 C 1244 1242 0 528.00pF 198.00pF 339.84pF 0.1451 379.09 325.87 528.00 198.00  

CPC102
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC102 F3 T 2 2 100.0  

Pin Nail Net Name
1 1257 P_GT_COMPA_10
2 1244 P_GT_FBA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1502 CPC102 47.00pF 47.00pF 2 C 1257 1244 0 75.20pF 28.20pF 47.12pF 0.0716 109.40 88.093 75.200 28.200  

CPC103
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC103 F3 T 2 2 100.0  

Pin Nail Net Name
1 1257 P_GT_COMPA_10
2 1243 P_GT_FBA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1556 CPC103 2200.0pF 2200.0pF 0 C 1257 1243 0 3520.0pF 1320.0pF 2071.5pF 2.2964 159.67 109.08 3520.0 1320.0  

CPC104
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC104 F3 T 2 2 100.0  

Pin Nail Net Name
1 1276 P_VCORE_FB_10
2 1274 P_VCORE_DIFF_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1535 CPC104 820.00pF 820.00pF 2 C 1276 1274 0 1312.00pF 492.00pF 817.29pF 2.0150 67.825 53.811 1312.0 492.00  

CPC105
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC105 F3 T 2 2 100.0  

Pin Nail Net Name
1 1275 P_VCORE_COMP_10
2 1276 P_VCORE_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1503 CPC105 47.00pF 47.00pF 2 C 1275 1276 0 75.20pF 28.20pF 47.01pF 0.0257 304.75 243.96 75.200 28.200  

CPC106
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC106 F3 T 2 2 100.0  

Pin Nail Net Name
1 1275 P_VCORE_COMP_10
2 1277 P_VCORE_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1557 CPC106 2200.0pF 2200.0pF 0 C 1275 1277 0 3520.0pF 1320.0pF 2110.7pF 2.1779 168.35 121.02 3520.0 1320.0  

CPC107
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC107 F3 T 2 2 100.0  

Pin Nail Net Name
1 1252 P_VCORE_VCC5_20
2 1233 DGND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1781 CPC107 1.000uF 1.000uF 0 C 1252 1233 0 1.600uF 0.600uF 1.030uF 0.0002 955.81 829.26 1.6000 0.6000  

CPC108
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC108 F3 T 2 2 100.0  

Pin Nail Net Name
1 1264 P_GT_CSP2A_10
2 1322 P_GT_CSN2A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1642 CPC108 0.1000uF 0.1000uF 0 C 1264 1322 0 0.1600uF 0.0600uF 0.1000uF 0.0001 237.18 204.46 0.1600 0.0600  

CPC109
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC109 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1253 P_VCORE_VRMP_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1573 CPC109 0.01000uF 0.01000uF 2 C 1233 1253 0 0.01600uF 0.00600uF 0.01000uF 0.0000 324.40 323.31 0.0200 0.0100  

CPC110
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC110 F3 T 2 2 100.0  

Pin Nail Net Name
1 1259 P_GT_CSP1A_10
2 1301 P_GT_CSN1A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1646 CPC110 0.1000uF 0.1000uF 0 C 1259 1301 0 0.1600uF 0.0600uF 0.1000uF 0.0001 258.42 199.43 0.1600 0.0600  

CPC115
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC115 F3 T 2 2 100.0  

Pin Nail Net Name
1 1267 P_VCORE_CSP2_10
2 1288 P_VCORE_CSN2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1650 CPC115 0.1000uF 0.1000uF 0 C 1267 1288 0 0.1600uF 0.0600uF 0.0900uF 0.0001 238.37 161.02 0.1600 0.0600  

CPC116
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC116 F3 T 2 2 100.0  

Pin Nail Net Name
1 1266 P_VCORE_CSP1_10
2 1320 P_VCORE_CSN1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1651 CPC116 0.1000uF 0.1000uF 0 C 1266 1320 0 0.1600uF 0.0600uF 0.1000uF 0.0001 288.23 230.82 0.1600 0.0600  

CPC118
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC118 F3 T 2 2 100.0  

Pin Nail Net Name
1 1270 P_VCORE_CSP3_10
2 1269 P_VCORE_CSN3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1635 CPC118 0.1000uF 0.1000uF 0 C 1270 1269 0 0.1600uF 0.0600uF 0.1000uF 0.0000 595.24 487.57 0.1600 0.0600  

CPC121
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC121 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1248 P_VCORE_IOUT_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1533 CPC121 470.00pF 470.00pF 2 C 1233 1248 0 752.00pF 282.00pF 470.10pF 0.3367 232.64 186.22 752.00 282.00  

CPC122
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC122 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1263 P_GT_TMA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1633 CPC122 0.1000uF 0.1000uF 1 C 1 1263 0 0.1600uF 0.0600uF 0.1000uF 0.0001 302.01 234.38 0.1600 0.0600  

CPC123
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC123 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1255 P_GT_IOUTA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1534 CPC123 470.00pF 470.00pF 2 C 1233 1255 0 752.00pF 282.00pF 469.73pF 0.4190 186.96 149.35 752.00 282.00  

CPC124
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC124 F3 T 2 2 100.0 Parallel CPC114

Pin Nail Net Name
1 1289 P_GT_CSCOMPA_10
2 1260 P_GT_CSSUMA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1558 CPC124/CPC114 2200.0pF 2380.0pF 0 C 1289 1260 0 3808.0pF 1428.0pF 1755.6pF 18.940 20.944 5.7660 3808.0 1428.0  

CPC126
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC126 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1265 P_VCORE_TM_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1668 CPC126 0.1000uF 0.1000uF 1 C 1 1265 0 0.1600uF 0.0600uF 0.1000uF 0.0000 600.78 492.39 0.1600 0.0600  

CPC128
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC128 F3 T 2 2 100.0 Parallel CPC117

Pin Nail Net Name
1 1317 P_VCORE_CSCOMP_10
2 1283 P_VCORE_CSSUM_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1561 CPC128/CPC117 3300.0pF 3630.0pF 0 C 1317 1283 0 5808.0pF 2178.0pF 2568.9pF 51.460 11.757 2.5320 5808.0 2178.0  

CPC132
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC132 F3 T 2 2 100.0  

Pin Nail Net Name
1 1051 H_VSS_SENSE
2 1247 P_VCORE_VSN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1547 CPC132 1000.0pF 1000.0pF 2 C 1051 1247 0 1600.0pF 600.0pF 1475.7pF 2.0257 82.276 20.453 1600.0 600.00  

CPC133
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC133 F3 T 2 2 100.0  

Pin Nail Net Name
1 1051 H_VSS_SENSE
2 1044 H_VCC_SENSE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1548 CPC133 1000.0pF 1000.0pF 2 C 1051 1044 948 1600.0pF 600.0pF 1082.6pF 1.3291 125.40 121.03 1600.0 600.00  

CPC137
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC137 F3 T 2 2 100.0  

Pin Nail Net Name
1 1061 H_GT_VSS_SENSE
2 1245 P_GT_VSNA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1549 CPC137 1000.0pF 1000.0pF 2 C 1061 1245 0 1600.0pF 600.0pF 1484.5pF 0.9464 176.10 40.687 1600.0 600.00  

CPC138
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC138 F3 T 2 2 100.0  

Pin Nail Net Name
1 1061 H_GT_VSS_SENSE
2 1046 H_GT_VCC_SENSE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1550 CPC138 1000.0pF 1000.0pF 2 C 1061 1046 1043 1600.0pF 600.0pF 1025.2pF 1.7278 96.461 82.031 1600.0 600.00  

CPC139
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC139 F3 T 2 2 100.0  

Pin Nail Net Name
1 1281 P_VCORE_CSP4_10
2 1286 P_VCORE_CSN4_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1675 CPC139 0.1000uF 0.1000uF 0 C 1281 1286 0 0.1600uF 0.0600uF 0.1000uF 0.0001 218.10 174.55 0.1600 0.0600  

CPC140
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC140 F2 T 2 2 100.0  

Pin Nail Net Name
1 1332 P_VCORE_VCC1_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1761 CPC140 1.000uF 1.000uF 0 C 1 1332 0 1.600uF 0.600uF 0.890uF 0.0007 232.50 133.07 1.6000 0.6000  

CPC141
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC141 E2 T 2 2 100.0  

Pin Nail Net Name
1 1034 P_VCORE_BST2_R_20
2 1024 P_VCORE_PHASE2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1692 CPC141 0.1000uF 0.1000uF 0 C 1034 1024 0 0.1600uF 0.0600uF 0.0900uF 0.0002 104.65 64.853 0.1600 0.0600  

CPC142
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC142 E2 T 2 2 100.0  

Pin Nail Net Name
1 1036 P_VCORE_VCC2_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1762 CPC142 1.000uF 1.000uF 0 C 1 1036 0 1.600uF 0.600uF 0.870uF 0.0007 236.75 128.52 1.6000 0.6000  

CPC143
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC143 E1 T 2 2 100.0  

Pin Nail Net Name
1 1014 P_VCORE_BST3_R_20
2 1023 P_VCORE_PHASE3_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1693 CPC143 0.1000uF 0.1000uF 0 C 1014 1023 0 0.1600uF 0.0600uF 0.0900uF 0.0002 102.98 63.751 0.1600 0.0600  

CPC144
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC144 E2 T 2 2 100.0  

Pin Nail Net Name
1 1028 P_VCORE_VCC3_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1763 CPC144 1.000uF 1.000uF 0 C 1 1028 0 1.600uF 0.600uF 0.870uF 0.0007 242.25 129.10 1.6000 0.6000  

CPC145
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC145 F2 T 2 2 100.0  

Pin Nail Net Name
1 1336 P_VCORE_BST1_R_20
2 1331 P_VCORE_PHASE1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1694 CPC145 0.1000uF 0.1000uF 0 C 1336 1331 0 0.1600uF 0.0600uF 0.0900uF 0.0002 77.241 52.880 0.1600 0.0600  

CPC193
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC193 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1236 P_VCORE_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1712 CPC193 0.1000uF 0.1000uF 0 C 1233 1236 2 0.1600uF 0.0600uF 0.1000uF 0.0001 194.26 160.38 0.1600 0.0600  

CPC194
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC194 E1 T 2 2 100.0  

Pin Nail Net Name
1 1029 P_VCORE_VCC4_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1770 CPC194 1.000uF 1.000uF 0 C 1 1029 0 1.600uF 0.600uF 0.840uF 0.0007 243.51 118.22 1.6000 0.6000  

CPC199
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC199 E1 T 2 2 100.0  

Pin Nail Net Name
1 1013 P_VCORE_BST4_R_20
2 949 P_VCORE_PHASE4_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1715 CPC199 0.1000uF 0.1000uF 0 C 1013 949 0 0.1600uF 0.0600uF 0.0900uF 0.0002 78.958 49.312 0.1600 0.0600  

CPC201
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC201 F3 T 2 2 100.0  

Pin Nail Net Name
1 1290 P_GT_VCC1_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1773 CPC201 1.000uF 1.000uF 0 C 1 1290 0 1.600uF 0.600uF 0.880uF 0.0006 271.10 151.30 1.6000 0.6000  

CPC202
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC202 F2 T 2 2 100.0  

Pin Nail Net Name
1 1310 P_GT_VCC2_R_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1774 CPC202 1.000uF 1.000uF 0 C 1 1310 0 1.600uF 0.600uF 0.870uF 0.0007 224.72 121.97 1.6000 0.6000  

CPC203
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC203 F3 T 2 2 100.0  

Pin Nail Net Name
1 1295 P_GT_BST1_R_20
2 1308 P_GT_PHASE1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1716 CPC203 0.1000uF 0.1000uF 0 C 1295 1308 0 0.1600uF 0.0600uF 0.0900uF 0.0000 347.50 209.36 0.1600 0.0600  

CPC204
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC204 F2 T 2 2 100.0  

Pin Nail Net Name
1 1313 P_GT_BST2_R_20
2 1323 P_GT_PHASE2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1717 CPC204 0.1000uF 0.1000uF 0 C 1313 1323 0 0.1600uF 0.0600uF 0.0900uF 0.0001 130.77 81.351 0.1600 0.0600  

CPC412
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC412 A1 T 2 2 100.0 Parallel CPC546

Pin Nail Net Name
1 2 +3V
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1806 CPC412/CAU1C2 10.00uF 10.20uF 4 C 1 2 0 16.32uF 6.12uF 10.67uF 0.0381 44.572 39.755 16.320 6.1200  

CPC414
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC414 A2 T 2 2 100.0  

Pin Nail Net Name
1 793 +3V_ATX
2 98 P_3V_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1671 CPC414 0.1000uF 0.1000uF 0 C 793 98 0 0.1600uF 0.0600uF 0.1500uF 0.0000 333.58 37.325 0.1600 0.0600  

CPC415
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC415 A2 T 2 2 100.0  

Pin Nail Net Name
1 99 P_+3V_OV_G1_10
2 100 P_+3V_OV_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1571 CPC415 0.01000uF 0.01000uF 1 C 100 99 0 0.01600uF 0.00600uF 0.01000uF 0.0000 373.25 237.37 0.0200 0.0100  

CPC418
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC418 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 525 P_+3V_OV_ER_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1711 CPC418 0.1000uF 0.1000uF 1 C 1 525 0 0.1600uF 0.0600uF 0.1000uF 0.0001 261.65 208.43 0.1600 0.0600  

CPC419
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC419 B2 T 2 2 100.0 Parallel CEC19

Pin Nail Net Name
1 793 +3V_ATX
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1795 CPC419/CEC19/ 10.00uF 10.10uF 0 C 1 793 0 16.16uF 6.06uF 8.19uF 0.0033 514.00 216.34 16.160 6.0600  

CPC530
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC530 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1160 P_VDDQ_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1559 CPC530 3300.0pF 3300.0pF 0 C 1 1160 0 5280.0pF 1980.0pF 3451.6pF 9.8656 55.749 49.721 5280.0 1980.0  

CPC531
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC531 F4 T 2 2 100.0  

Pin Nail Net Name
1 1167 P_VDDQ_OFS_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1592 CPC531 0.0220uF 0.0220uF 0 C 1 1167 0 0.0352uF 0.0132uF 0.0200uF 0.0001 63.794 39.263 0.0400 0.0100  

CPC532
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC532 F4 T 2 2 100.0  

Pin Nail Net Name
1 1177 P_VDDQ_VCC_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1777 CPC532 1.000uF 1.000uF 0 C 1 1177 0 1.600uF 0.600uF 0.860uF 0.0006 267.38 141.66 1.6000 0.6000  

CPC536
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC536 F4 T 2 2 100.0  

Pin Nail Net Name
1 1147 P_VDDQ_PHASE_20
2 1174 P_VDDQ_BOOT_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1639 CPC536 0.1000uF 0.1000uF 0 C 1147 1174 0 0.1600uF 0.0600uF 0.0900uF 0.0001 139.53 86.425 0.1600 0.0600  

CPC537
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC537 F4 T 2 2 100.0  

Pin Nail Net Name
1 1158 P_VDDQ_FB_C_10
2 1159 P_VDDQ_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1599 CPC537 0.0680uF 0.0680uF 0 C 1159 1158 1168 0.1088uF 0.0408uF 0.0700uF 0.0003 41.020 35.569 0.1100 0.0400  

CPC539
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC539 C4 T 2 2 100.0  

Pin Nail Net Name
1 710 P_VTT_DDR_REFIN_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1684 CPC539 0.1000uF 0.1000uF 0 C 1 710 0 0.1600uF 0.0600uF 0.1000uF 0.0001 200.60 171.35 0.1600 0.0600  

CPC549
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC549 C4 T 2 2 100.0 Parallel CD3C5

Pin Nail Net Name
1 733 VTT_DDR
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1834 CPC549/CD3C5/ 22.00uF 44.00uF 4 C 1 733 0 57.20uF 28.60uF 29.75uF 0.2570 18.545 1.4870 57.200 28.600  

CPC552
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC552 C4 T 2 2 100.0  

Pin Nail Net Name
1 708 P_VTT_DDR_REOUT_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1605 CPC552 0.1000uF 0.1000uF 0 C 1 708 0 0.1600uF 0.0600uF 0.1000uF 0.0001 187.76 132.64 0.1600 0.0600  

CPC605
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC605 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 355 P_+5VSB_ATX_OV_E_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1696 CPC605 0.1000uF 0.1000uF 1 C 1 355 0 0.1600uF 0.0600uF 0.1000uF 0.0001 249.29 197.79 0.1600 0.0600  

CPC606
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC606 B4 T 2 2 100.0  

Pin Nail Net Name
1 368 P_+5VSB_ATX_OV_B_10
2 358 P_+5VSB_ATX_OV_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1505 CPC606 100.00pF 100.00pF 2 C 358 368 0 160.00pF 60.00pF 100.13pF 0.0912 182.73 146.67 160.00 60.000  

CPC607
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC607 B4 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 367 P_5VSB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1600 CPC607 0.0680uF 0.0680uF 0 C 797 367 0 0.1088uF 0.0408uF 0.0600uF 0.0001 192.47 132.60 0.1100 0.0400  

CPC613
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC613 B4 T 2 2 100.0  

Pin Nail Net Name
1 405 +5VSB
2 380 P_5VSB_GATE_RC_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1570 CPC613 0.01000uF 0.01000uF 0 C 405 380 0 0.01600uF 0.00600uF 0.01000uF 0.0000 112.66 83.523 0.0200 0.0100  

CPC630
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC630 B4 T 2 2 100.0  

Pin Nail Net Name
1 366 P_5VSB_Q2_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1597 CPC630 0.0470uF 0.0470uF 0 C 1 366 0 0.0752uF 0.0282uF 0.0700uF 0.0000 158.89 68.121 0.0800 0.0300  

CPC701
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC701 B2 T 2 2 100.0 Parallel CEC36

Pin Nail Net Name
1 797 +5VSB_ATX
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1797 CPC701/CEC36/ 10.00uF 20.20uF 4 C 1 797 0 32.32uF 12.12uF 13.92uF 0.0562 59.854 10.640 32.320 12.120  

CPC715
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC715 B2 T 2 2 100.0 Parallel CL1U1C232

Pin Nail Net Name
1 399 +3VSB_ATX
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1825 CPC715/COU1C2 22.00uF 24.00uF 4 C 1 399 0 31.20uF 15.60uF 16.99uF 0.1792 14.508 2.5770 31.200 15.600  

CPC731
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC731 B4 T 2 2 100.0  

Pin Nail Net Name
1 391 P_+1_0V_A_BST_R_20
2 398 P_+1_0V_A_SW_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1664 CPC731 0.1000uF 0.1000uF 0 C 391 398 0 0.1600uF 0.0600uF 0.0900uF 0.0001 209.84 141.25 0.1600 0.0600  

CPC732
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC732 B4 T 2 2 100.0  

Pin Nail Net Name
1 401 +1_0V_A_VCC_20
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1786 CPC732 2.200uF 2.200uF 0 C 1 401 0 3.520uF 1.320uF 1.330uF 0.0019 188.76 2.0450 3.5200 1.3200  

CPC736
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC736 B4 T 2 2 100.0  

Pin Nail Net Name
1 400 P_+1_0V_A_VOUT_10
2 390 P_+1_0V_A_FBR_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1530 CPC736 220.00pF 220.00pF 2 C 400 390 0 352.00pF 132.00pF 219.99pF 0.3003 122.11 97.675 352.00 132.00  

CPC740
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC740 B3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 413 P_VCCST_VCCSFR_D1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1620 CPC740 0.1000uF 0.1000uF 0 C 1 413 0 0.1600uF 0.0600uF 0.1000uF 0.0002 104.57 77.863 0.1600 0.0600  

CPC751
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC751 D1 T 2 2 100.0  

Pin Nail Net Name
1 968 P_VCCSA_FB_C_10
2 957 P_VCCSA_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1598 CPC751 0.0680uF 0.0680uF 1 C 957 968 0 0.1088uF 0.0408uF 0.0700uF 0.0001 205.16 190.34 0.1100 0.0400  

CPC752
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC752 D2 T 2 2 100.0  

Pin Nail Net Name
1 950 P_VCCSA_PHASE_20
2 952 P_VCCSA_BOOT_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1623 CPC752 0.1000uF 0.1000uF 0 C 950 952 0 0.1600uF 0.0600uF 0.0900uF 0.0001 241.26 138.27 0.1600 0.0600  

CPC757
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC757 D1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 967 P_VCCSA_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1560 CPC757 3300.0pF 3300.0pF 0 C 1 967 0 5280.0pF 1980.0pF 3354.9pF 13.619 40.386 33.652 5280.0 1980.0  

CPC759
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC759 D1 T 2 2 100.0  

Pin Nail Net Name
1 955 P_VCCSA_OFS_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1593 CPC759 0.0220uF 0.0220uF 0 C 1 955 0 0.0352uF 0.0132uF 0.0200uF 0.0001 33.846 23.681 0.0400 0.0100  

CPC760
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC760 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 388 P_+1_8V_A_PG_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1785 CPC760 1.000uF 1.000uF 0 C 1 388 0 1.600uF 0.600uF 0.630uF 0.0006 270.61 17.830 1.6000 0.6000  

CPC803
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC803 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1226 P_+12V_3V_EN_B1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1630 CPC803 0.1000uF 0.1000uF 0 C 1 1226 0 0.1600uF 0.0600uF 0.1000uF 0.0001 193.52 143.08 0.1600 0.0600  

CPC804
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC804 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1240 P_+12V_3V_EN_B2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1631 CPC804 0.1000uF 0.1000uF 0 C 1 1240 0 0.1600uF 0.0600uF 0.1000uF 0.0001 136.23 103.08 0.1600 0.0600  

CPC807
Device Loc Side Total Pin Tested Coverage (%) Comment
CPC807 F4 T 2 2 100.0  

Pin Nail Net Name
1 1235 P_VRM_PGD_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1543 CPC807 1000.0pF 1000.0pF 2 C 1 1235 0 1600.0pF 600.0pF 1000.7pF 2.3710 70.295 56.332 1600.0 600.00  

CAC1
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC1 B1 T 2 2 100.0  

Pin Nail Net Name
1 609 A_LINE_L
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1507 CAC1 100.00pF 100.00pF 2 C 628 609 0 160.00pF 60.00pF 100.46pF 1.4330 11.631 9.4110 160.00 60.000  

CAC13
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC13 A1 T 2 2 100.0  

Pin Nail Net Name
1 61 A_HPOUT_L
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1508 CAC13 100.00pF 100.00pF 2 C 628 61 0 160.00pF 60.00pF 99.78pF 0.0371 449.25 357.43 160.00 60.000  

CAC14
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC14 A1 T 2 2 100.0  

Pin Nail Net Name
1 59 A_HPOUT_R
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1509 CAC14 100.00pF 100.00pF 2 C 628 59 0 160.00pF 60.00pF 99.79pF 0.0525 317.40 252.58 160.00 60.000  

CAC17
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC17 A1 T 2 2 100.0  

Pin Nail Net Name
1 17 A_LINE_L_L
2 32 A_LINE_L_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1809 CAC17 10.00uF 10.00uF 4 C 17 32 0 16.00uF 6.00uF 7.91uF 0.0185 90.090 34.392 16.000 6.0000  

CAC18
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC18 A1 T 2 2 100.0  

Pin Nail Net Name
1 613 A_LINE_R_L
2 33 A_LINE_R_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1810 CAC18 10.00uF 10.00uF 4 C 613 33 0 16.00uF 6.00uF 7.85uF 0.0183 90.936 33.710 16.000 6.0000  

CAC19
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC19 A1 T 2 2 100.0  

Pin Nail Net Name
1 20 A_MIC1_L_L
2 30 A_MIC1_L_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1792 CAC19 4.700uF 4.700uF 4 C 20 30 0 7.520uF 2.820uF 3.510uF 0.0149 52.503 15.387 7.5200 2.8200  

CAC2
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC2 C1 T 2 2 100.0  

Pin Nail Net Name
1 629 A_LINE_R
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1512 CAC2 100.00pF 100.00pF 2 C 628 629 0 160.00pF 60.00pF 92.15pF 5.8754 2.8370 1.8240 160.00 60.000  

CAC20
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC20 A1 T 2 2 100.0  

Pin Nail Net Name
1 23 A_MIC1_R_L
2 31 A_MIC1_R_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1793 CAC20 4.700uF 4.700uF 4 C 23 31 0 7.520uF 2.820uF 3.380uF 0.0357 21.951 5.2750 7.5200 2.8200  

CAC21
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC21 A1 T 2 2 100.0  

Pin Nail Net Name
1 7 A_FMIC1_L_L
2 28 A_FMIC1_L_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1813 CAC21 10.00uF 10.00uF 4 C 7 28 0 16.00uF 6.00uF 8.04uF 0.0192 86.746 35.405 16.000 6.0000  

CAC22
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC22 A1 T 2 2 100.0  

Pin Nail Net Name
1 19 A_FMIC1_R_L
2 29 A_FMIC1_R_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1814 CAC22 10.00uF 10.00uF 4 C 19 29 0 16.00uF 6.00uF 7.81uF 0.0295 56.467 20.420 16.000 6.0000  

CAC24
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC24 B1 T 2 2 100.0 Parallel CAC23

Pin Nail Net Name
1 618 A_CGND
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1641 CAC24/CAC23/N 0.1000uF 0.1000uF 0 C 618 628 0 0.1600uF 0.0600uF 0.0800uF 0.0000 351.33 172.51 0.1600 0.0600  

CAC251
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC251 A1 T 2 2 100.0  

Pin Nail Net Name
1 66 MUTE_POP_EN
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1783 CAC251 1.000uF 1.000uF 0 C 1 66 0 1.600uF 0.600uF 0.620uF 0.0012 141.17 6.6580 1.6000 0.6000  

CAC252
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC252 A1 T 2 2 100.0  

Pin Nail Net Name
1 67 MUTE_POP
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1817 CAC252 10.00uF 10.00uF 4 C 1 67 0 16.00uF 6.00uF 6.49uF 0.0239 69.749 6.8770 16.000 6.0000  

CAC27
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC27 A1 T 2 2 100.0  

Pin Nail Net Name
1 60 A_JD_FRONT
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1513 CAC27 100.00pF 100.00pF 2 C 628 60 0 160.00pF 60.00pF 99.92pF 0.0238 701.56 560.08 160.00 60.000  

CAC3
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC3 B1 T 2 2 100.0  

Pin Nail Net Name
1 612 A_LOUT_L
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1514 CAC3 100.00pF 100.00pF 2 C 628 612 0 160.00pF 60.00pF 99.85pF 0.5221 31.925 25.446 160.00 60.000  

CAC37
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC37 A1 T 2 2 100.0 Parallel CAC15

Pin Nail Net Name
1 38 A_FMIC1_L
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1590 CAC37/CAC15 0.01000uF 0.01000uF 0 C 38 628 0 0.01600uF 0.00600uF 0.01000uF 0.0000 89.305 78.214 0.0200 0.0100  

CAC38
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC38 A1 T 2 2 100.0 Parallel CAC16

Pin Nail Net Name
1 58 A_FMIC1_R
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1591 CAC38/CAC16 0.01000uF 0.01000uF 0 C 58 628 0 0.01600uF 0.00600uF 0.01000uF 0.0000 198.68 153.04 0.0200 0.0100  

CAC4
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC4 B1 T 2 2 100.0  

Pin Nail Net Name
1 627 A_LOUT_R
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1515 CAC4 100.00pF 100.00pF 2 C 628 627 0 160.00pF 60.00pF 100.77pF 2.1858 7.6250 6.2170 160.00 60.000  

CAC5
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC5 B1 T 2 2 100.0  

Pin Nail Net Name
1 619 A_MIC1_L
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1516 CAC5 100.00pF 100.00pF 2 C 628 619 0 160.00pF 60.00pF 100.44pF 2.6770 6.2260 5.0350 160.00 60.000  

CAC6
Device Loc Side Total Pin Tested Coverage (%) Comment
CAC6 B1 T 2 2 100.0  

Pin Nail Net Name
1 621 A_MIC1_R
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1517 CAC6 100.00pF 100.00pF 2 C 628 621 0 160.00pF 60.00pF 98.92pF 2.0334 8.1970 6.3800 160.00 60.000  

CACE1
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE1 A1 T 2 2 100.0  

Pin Nail Net Name
1 52 A_LOUT_L_C
2 64 A_LOUT_L_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1858 CACE1 100.00uF 100.00uF 4 C 52 64 0 130.00uF 70.00uF 103.13uF 0.3159 31.661 28.363 130.00 70.000  

CACE10
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE10 A1 T 2 2 100.0  

Pin Nail Net Name
1 41 A_HPOUT_R_C
2 40 A_HPOUT_R_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1855 CACE10 100.00uF 100.00uF 4 C 41 40 0 130.00uF 70.00uF 99.77uF 0.2939 34.027 33.770 130.00 70.000  

CACE2
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE2 A1 T 2 2 100.0  

Pin Nail Net Name
1 54 A_LOUT_R_C
2 18 A_LOUT_R_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1856 CACE2 100.00uF 100.00uF 4 C 54 18 0 130.00uF 70.00uF 98.18uF 0.0000 99999 99999 130.00 70.000  

CACE9
Device Loc Side Total Pin Tested Coverage (%) Comment
CACE9 A1 T 2 2 100.0  

Pin Nail Net Name
1 46 A_HPOUT_L_C
2 39 A_HPOUT_L_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1857 CACE9 100.00uF 100.00uF 4 C 46 39 0 130.00uF 70.00uF 103.28uF 0.3647 27.419 24.418 130.00 70.000  

CAU1C238
Device Loc Side Total Pin Tested Coverage (%) Comment
CAU1C238 A1 T 2 2 100.0 Parallel CAU1C38

Pin Nail Net Name
1 45 +5VA
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1808 CAU1C238/CAU1 10.00uF 10.20uF 4 C 628 45 0 16.32uF 6.12uF 7.66uF 0.0278 61.174 18.446 16.320 6.1200  

CAU1C27
Device Loc Side Total Pin Tested Coverage (%) Comment
CAU1C27 A1 T 2 2 100.0 Parallel CAU1C227

Pin Nail Net Name
1 42 A_VREF
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1807 CAU1C27/CAU1C 10.00uF 10.00uF 4 C 628 42 0 16.00uF 6.00uF 8.07uF 0.0000 99999 99999 16.000 6.0000  

CAU1C3
Device Loc Side Total Pin Tested Coverage (%) Comment
CAU1C3 A1 T 2 2 100.0  

Pin Nail Net Name
1 48 A_REGREF
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1819 CAU1C3 10.00uF 10.00uF 4 C 1 48 0 16.00uF 6.00uF 7.78uF 0.0180 92.640 32.999 16.000 6.0000  

CAU2C4
Device Loc Side Total Pin Tested Coverage (%) Comment
CAU2C4 A1 T 2 2 100.0  

Pin Nail Net Name
1 27 -12VA
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1802 CAU2C4 10.00uF 10.00uF 4 C 27 628 0 16.00uF 6.00uF 6.56uF 0.0127 131.05 14.574 16.000 6.0000  

CESDC14
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC14 A3 T 2 2 100.0  

Pin Nail Net Name
1 140 S_VCORE_SHDN__10_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1536 CESDC14 1000.0pF 1000.0pF 2 C 1 140 0 1600.0pF 600.0pF 1001.2pF 1.4413 115.64 92.793 1600.0 600.00  

CESDC5
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC5 C3 T 2 2 100.0 Parallel CSC26

Pin Nail Net Name
1 1 GND
2 410 S_VCCST_PWRGD

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1504 CESDC5/CSC26/ 100.00pF 100.00pF 2 C 1 410 0 160.00pF 60.00pF 100.05pF 0.0831 200.51 160.62 160.00 60.000  

CESDC7
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC7 A3 T 2 2 100.0 Parallel CSC24

Pin Nail Net Name
1 271 S_PWROK
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1537 CESDC7/CSC24/ 1000.0pF 1000.0pF 2 C 1 271 0 1600.0pF 600.0pF 1001.8pF 1.8981 87.807 70.569 1600.0 600.00  

CESDC8
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC8 A3 T 2 2 100.0  

Pin Nail Net Name
1 154 O_IOPWRBTN_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1538 CESDC8 1000.0pF 1000.0pF 2 C 1 154 0 1600.0pF 600.0pF 999.7pF 0.9040 184.36 147.37 1600.0 600.00  

CESDC9
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDC9 A3 T 2 2 100.0  

Pin Nail Net Name
1 133 O_RSTCON_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1539 CESDC9 1000.0pF 1000.0pF 2 C 1 133 0 1600.0pF 600.0pF 1001.2pF 2.5295 65.888 52.869 1600.0 600.00  

CESDO1C15
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDO1C15 B1 T 2 2 100.0  

Pin Nail Net Name
1 588 O1_PME_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1518 CESDO1C15 120.00pF 120.00pF 2 C 1 588 0 192.00pF 72.00pF 121.15pF 1.3725 14.572 11.936 192.00 72.000  

CESDO1C3
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDO1C3 B1 T 2 2 100.0 Parallel CTMC4

Pin Nail Net Name
1 83 S_PLTRST_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1540 CESDO1C3/CL1C 1000.0pF 1000.0pF 2 C 1 83 0 1600.0pF 600.0pF 1002.9pF 1.5868 105.03 84.633 1600.0 600.00  

CESDOC205
Device Loc Side Total Pin Tested Coverage (%) Comment
CESDOC205 A4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 345 HDLED-

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1697 CESDOC205 0.1000uF 0.1000uF 0 C 1 345 0 0.1600uF 0.0600uF 0.0800uF 0.0001 152.42 72.855 0.1600 0.0600  

CHC24
Device Loc Side Total Pin Tested Coverage (%) Comment
CHC24 C3 T 2 2 100.0 Parallel CHC7

Pin Nail Net Name
1 426 VCCST_VCCSFR
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1804 CHC24/CHC7/CH 10.00uF 14.90uF 4 C 1 426 0 23.84uF 8.94uF 12.48uF 0.0309 80.291 38.151 23.840 8.9400  

CHTC1
Device Loc Side Total Pin Tested Coverage (%) Comment
CHTC1 D3 T 2 2 100.0 Parallel COC217

Pin Nail Net Name
1 70 H_TR
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1613 CHTC1/COC217/ 0.1000uF 0.1000uF 0 C 1 70 0 0.1600uF 0.0600uF 0.0900uF 0.0001 282.79 187.41 0.1600 0.0600  

CO1C12
Device Loc Side Total Pin Tested Coverage (%) Comment
CO1C12 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 608 O_5V_IN_2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1506 CO1C12 100.00pF 100.00pF 2 C 1 608 0 160.00pF 60.00pF 95.85pF 3.3128 5.0310 3.6070 160.00 60.000  

CO1C32
Device Loc Side Total Pin Tested Coverage (%) Comment
CO1C32 B1 T 2 2 100.0  

Pin Nail Net Name
1 607 O_12V_IN_1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1541 CO1C32 1000.0pF 1000.0pF 2 C 1 607 0 1600.0pF 600.0pF 1000.7pF 1.2294 135.56 108.64 1600.0 600.00  

CO1C34
Device Loc Side Total Pin Tested Coverage (%) Comment
CO1C34 B1 T 2 2 100.0  

Pin Nail Net Name
1 606 O_5V_IN_1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1542 CO1C34 1000.0pF 1000.0pF 2 C 1 606 0 1600.0pF 600.0pF 1001.6pF 1.7973 92.733 74.480 1600.0 600.00  

COC1
Device Loc Side Total Pin Tested Coverage (%) Comment
COC1 F1 T 2 2 100.0  

Pin Nail Net Name
1 1344 O_KB_DATA_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1527 COC1 150.00pF 150.00pF 2 C 1 1344 0 240.00pF 90.00pF 149.59pF 0.8586 29.119 23.134 240.00 90.000  

COC2
Device Loc Side Total Pin Tested Coverage (%) Comment
COC2 F1 T 2 2 100.0  

Pin Nail Net Name
1 1340 O_KB_CLK_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1528 COC2 150.00pF 150.00pF 2 C 1 1340 0 240.00pF 90.00pF 145.46pF 0.3776 66.212 48.959 240.00 90.000  

COC202
Device Loc Side Total Pin Tested Coverage (%) Comment
COC202 A4 T 2 2 100.0  

Pin Nail Net Name
1 343 O_RSTCON__P
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1644 COC202 0.1000uF 0.1000uF 0 C 1 343 0 0.1600uF 0.0600uF 0.1100uF 0.0000 335.17 322.27 0.1600 0.0600  

COC206
Device Loc Side Total Pin Tested Coverage (%) Comment
COC206 A4 T 2 2 100.0  

Pin Nail Net Name
1 569 PWRBTN_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1544 COC206 1000.0pF 1000.0pF 2 C 1 569 0 1600.0pF 600.0pF 998.3pF 0.2855 583.82 465.08 1600.0 600.00  

COC301
Device Loc Side Total Pin Tested Coverage (%) Comment
COC301 F3 T 2 2 100.0  

Pin Nail Net Name
1 1304 O_CPUFANIN_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1649 COC301 0.1000uF 0.1000uF 0 C 1 1304 0 0.1600uF 0.0600uF 0.1000uF 0.0001 257.09 216.14 0.1600 0.0600  

COC311
Device Loc Side Total Pin Tested Coverage (%) Comment
COC311 C2 T 2 2 100.0  

Pin Nail Net Name
1 669 O_CHAFANIN1_R
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1653 COC311 0.1000uF 0.1000uF 0 C 1 669 0 0.1600uF 0.0600uF 0.1000uF 0.0001 268.55 233.98 0.1600 0.0600  

COC760
Device Loc Side Total Pin Tested Coverage (%) Comment
COC760 B2 T 2 2 100.0  

Pin Nail Net Name
1 532 N16715606
2 534 O_DEEP_S5_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1656 COC760 0.1000uF 0.1000uF 0 C 534 532 549 0.1600uF 0.0600uF 0.0800uF 0.0001 116.68 56.551 0.1600 0.0600  

COC761
Device Loc Side Total Pin Tested Coverage (%) Comment
COC761 B2 T 2 2 100.0  

Pin Nail Net Name
1 399 +3VSB_ATX
2 534 O_DEEP_S5_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1657 COC761 0.1000uF 0.1000uF 0 C 399 534 532 0.1600uF 0.0600uF 0.0900uF 0.0001 233.64 143.81 0.1600 0.0600  

COTC1
Device Loc Side Total Pin Tested Coverage (%) Comment
COTC1 A4 T 2 2 100.0  

Pin Nail Net Name
1 576 O_TR_MB
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1655 COTC1 0.1000uF 0.1000uF 0 C 1 576 0 0.1600uF 0.0600uF 0.0900uF 0.0001 221.30 143.04 0.1600 0.0600  

COU1C31
Device Loc Side Total Pin Tested Coverage (%) Comment
COU1C31 B1 T 2 2 100.0 Parallel COU1C231

Pin Nail Net Name
1 1 GND
2 589 O_+1_8VA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1666 COU1C31/COU1C 0.1000uF 0.1000uF 0 C 1 589 0 0.1600uF 0.0600uF 0.0800uF 0.0001 218.57 104.17 0.1600 0.0600  

COU1C45
Device Loc Side Total Pin Tested Coverage (%) Comment
COU1C45 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 596 +3V_BAT_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1676 COU1C45 0.1000uF 0.1000uF 0 C 1 596 0 0.1600uF 0.0600uF 0.0800uF 0.0003 63.904 27.378 0.1600 0.0600  

COU1C53
Device Loc Side Total Pin Tested Coverage (%) Comment
COU1C53 B1 T 2 2 100.0 Parallel COU1C253

Pin Nail Net Name
1 1 GND
2 615 O_VREF_SIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1702 COU1C53/COU1C 0.1000uF 0.1000uF 0 C 1 615 0 0.1600uF 0.0600uF 0.1000uF 0.0000 438.21 378.48 0.1600 0.0600  

CPCE103
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE103 E2 T 2 2 100.0 Parallel CPC166

Pin Nail Net Name
1 948 VCORE
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1867 CPCE103/CPC16 560.00uF 3064.0uF 8 C 1 948 0 3983.2uF 2757.6uF 2828.6uF 23.634 8.6430 1.0010 3983.2 2757.6  

CPCE109
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE109 E1 T 2 2 100.0 Parallel CPC756

Pin Nail Net Name
1 1325 P_VCORE_L+12V_S
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1863 CPCE109/CPC23 270.00uF 1087.0uF 8 C 1 1325 0 1413.1uF 978.3uF 1050.5uF 3.2777 22.109 7.3420 1413.1 978.30  

CPCE207
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE207 E3 T 2 2 100.0 Parallel CPC224

Pin Nail Net Name
1 1043 VCCGT
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1872 CPCE207/CPC21 560.00uF 2460.0uF 8 C 1 1043 0 3198.0uF 2214.0uF 2305.4uF 0.0000 99999 99999 3198.0 2214.0  

CPCE516
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE516 D4 T 2 2 100.0 Parallel CHC14

Pin Nail Net Name
1 1148 VDDQ
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1877 CPCE516/CHC14 560.00uF 1711.0uF 8 C 1 1148 0 2224.3uF 1539.9uF 1653.7uF 4.8425 23.555 7.8350 2224.3 1539.9  

CPCE518
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE518 F4 T 2 2 100.0 Parallel CPC548

Pin Nail Net Name
1 1150 P_VDDQ_REGIN_S
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1876 CPCE518/CPC54 560.00uF 570.00uF 4 C 1 1150 0 741.00uF 399.00uF 520.39uF 1.5987 35.653 25.310 741.00 399.00  

CPCE707
Device Loc Side Total Pin Tested Coverage (%) Comment
CPCE707 D2 T 2 2 100.0 Parallel CPC748

Pin Nail Net Name
1 946 VCCIO
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1880 CPCE707/CPCE3 560.00uF 1250.0uF 8 C 1 946 0 1625.0uF 1062.5uF 1093.0uF 4.0844 22.953 2.4890 1625.0 1062.5  

CSC3
Device Loc Side Total Pin Tested Coverage (%) Comment
CSC3 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 233 VCC_RTCEXT_CAP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1714 CSC3 0.1000uF 0.1000uF 0 C 1 233 0 0.1600uF 0.0600uF 0.1000uF 0.0001 200.00 149.21 0.1600 0.0600  

CSC59
Device Loc Side Total Pin Tested Coverage (%) Comment
CSC59 A3 T 2 2 100.0  

Pin Nail Net Name
1 114 S_RTCRST_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1779 CSC59 1.000uF 1.000uF 0 C 1 114 0 1.600uF 0.600uF 0.740uF 0.0015 114.56 32.015 1.6000 0.6000  

CSC60
Device Loc Side Total Pin Tested Coverage (%) Comment
CSC60 A3 T 2 2 100.0  

Pin Nail Net Name
1 115 S_SRTCRST_
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1769 CSC60 1.000uF 1.000uF 0 C 1 115 0 1.600uF 0.600uF 0.730uF 0.0022 77.068 19.855 1.6000 0.6000  

CUC750
Device Loc Side Total Pin Tested Coverage (%) Comment
CUC750 B4 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 374 N16718199

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1723 CUC750 0.220uF 0.220uF 0 C 107 374 0 0.352uF 0.132uF 0.200uF 0.0002 169.07 106.62 0.3500 0.1300  

CUCE1
Device Loc Side Total Pin Tested Coverage (%) Comment
CUCE1 A2 T 2 2 100.0 Parallel CEC10

Pin Nail Net Name
1 107 +5VSB_DUAL
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1859 CUCE1/CEC10/N 100.00uF 300.90uF 8 C 1 107 0 391.17uF 270.81uF 284.70uF 0.7964 25.189 5.8150 391.17 270.81  

CXCE1
Device Loc Side Total Pin Tested Coverage (%) Comment
CXCE1 B1 T 2 2 100.0 Parallel CPC312

Pin Nail Net Name
1 4 +12V
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1862 CXCE1/CPC312/ 270.00uF 270.10uF 4 C 1 4 0 351.13uF 189.07uF 281.63uF 1.4372 18.793 16.120 351.13 189.07