Resistor Tested Devices

RBR1 RBR2 RBR3 RL1R1 RL1R17 RL1R2 RL1R3 RL1R5 RL1R6 RL1R85
RD3R109 RD3R2 RD3R21 RD3R22 RD3R23 RD3R3 RD3R6 RD3R7 RD3R8 LAL1
LAL13 LAL14 LAL15 LAL16 LAL2 LAL3 LAL4 LAL5 LAL6 RAR1
RAR10 RAR100 RAR11 RAR2 RAR250 RAR251 RAR252 RAR253 RAR254 RAR255
RAR256 RAR257 RAR258 RAR259 RAR260 RAR269 RAR271 RAR273 RAR274 RAR3
RAR4 RAR8 RAR9 RAU2R1 RAU2R2 RAU2R6 RAU2R7 REATXR16 REATXR216 RGR129
RGR130 RGR131 RGR132 RGR133 RGR134 RGR135 RGR136 RGR151 RGR251 RGR69
RGR70 RHR1 RHR105 RHR202 RHR203 RHR208 RHR209 RHR217 RHR218 RHR52
RHR61 RHR90 RHR96 RHTR1 RO1R1 RO1R10 RO1R12 RO1R13 RO1R14 RO1R18
RO1R19 RO1R198 RO1R199 RO1R2 RO1R21 RO1R23 RO1R24 RO1R25 RO1R3 RO1R30
RO1R31 RO1R32 RO1R33 RO1R34 RO1R35 RO1R4 RO1R40 RO1R43 RO1R44 RO1R6
RO1R7 RO1R97 ROR202 ROR204 ROR217 ROR218 ROR300 ROR301 ROR302 ROR303
ROR310 ROR311 ROR312 ROR313 ROR402 ROR403 ROR404 ROR405 ROR406 ROR407
ROR760 ROR761 ROR762 ROR763 ROR766 ROR767 ROR769 ROR770 ROR771 ROR772
ROTR1 RPR101 RPR103 RPR104 RPR105 RPR106 RPR107 RPR109 RPR111 RPR112
RPR113 RPR117 RPR118 RPR122 RPR123 RPR125 RPR127 RPR128 RPR129 RPR130
RPR132 RPR133 RPR134 RPR135 RPR137 RPR138 RPR139 RPR140 RPR141 RPR143
RPR146 RPR147 RPR148 RPR149 RPR150 RPR153 RPR154 RPR155 RPR156 RPR157
RPR158 RPR159 RPR161 RPR163 RPR164 RPR168 RPR169 RPR172 RPR186 RPR187
RPR189 RPR195 RPR197 RPR198 RPR201 RPR202 RPR207 RPR210 RPR224 RPR225
RPR307 RPR323 RPR328 RPR407 RPR413 RPR415 RPR416 RPR418 RPR421 RPR426
RPR429 RPR431 RPR503 RPR504 RPR505 RPR508 RPR531 RPR533 RPR535 RPR537
RPR540 RPR542 RPR545 RPR546 RPR550 RPR551 RPR552 RPR553 RPR554 RPR556
RPR559 RPR560 RPR565 RPR567 RPR568 RPR599 RPR601 RPR603 RPR604 RPR605
RPR606 RPR607 RPR608 RPR609 RPR610 RPR611 RPR612 RPR613 RPR614 RPR615
RPR616 RPR617 RPR618 RPR619 RPR621 RPR622 RPR624 RPR625 RPR627 RPR628
RPR629 RPR630 RPR631 RPR632 RPR633 RPR634 RPR701 RPR702 RPR707 RPR708
RPR712 RPR713 RPR717 RPR718 RPR739 RPR740 RPR741 RPR743 RPR744 RPR755
RPR756 RPR759 RPR760 RPR762 RPR764 RPR767 RPR768 RPR769 RPR770 RPR779
RPR782 RPR801 RPR802 RPR803 RPR805 RPR808 RPR809 RPR812 RPR814 RPR815
RPR816 RPR817 RPR826 RPR827 RPR829 RPR830 RPR832 RPR837 RPTR101 RPTR102
RPTR103 RPTR104 RSR10 RSR100 RSR1000 RSR1001 RSR1002 RSR1003 RSR1004 RSR1005
RSR1006 RSR11 RSR118 RSR119 RSR120 RSR121 RSR122 RSR125 RSR127 RSR129
RSR134 RSR135 RSR14 RSR145 RSR152 RSR1607 RSR1628 RSR163 RSR1633 RSR1642
RSR1643 RSR1645 RSR1652 RSR1654 RSR1655 RSR1656 RSR166 RSR1666 RSR1667 RSR1668
RSR1669 RSR167 RSR1670 RSR1671 RSR1682 RSR1683 RSR1684 RSR1685 RSR1686 RSR1687
RSR1688 RSR1689 RSR1690 RSR1715 RSR1716 RSR1717 RSR1718 RSR1724 RSR1725 RSR1726
RSR1727 RSR1756 RSR1762 RSR1763 RSR1764 RSR1794 RSR1795 RSR1796 RSR18 RSR202
RSR22 RSR242 RSR304 RSR38 RSR4 RSR40 RSR43 RSR44 RSR49 RSR5
RSR50 RSR52 RSR569 RSR57 RSR570 RSR571 RSR573 RSR574 RSR60 RSR701
RSR73 RSR75 RSR801 RSR87 RSR9 RSR934 RSR99 RUR700 RUR702 RUR703
RUR730 RUR750 RUR751 RUR752 RUR753 RUR754 RUR755 RUR756 RUR757 RUR758
RUR759 RUR760 RUR761 RUR762 RUR763 RUR764 RUR765 RUR766 RUR767 RUR768

RBR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RBR1 B2 T 2 2 100.0  

Pin Nail Net Name
1 521 S_PME_
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1052 RBR1 8.200K 8.200K 2 R 549 521 0 9.020K 7.380K 8.280K 0.0037 74.771 67.279 9.0200 7.3800  

RBR2
Device Loc Side Total Pin Tested Coverage (%) Comment
RBR2 B2 T 2 2 100.0  

Pin Nail Net Name
1 678 N41678282
2 663 LS_COM1_RI1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1037 RBR2 8.200K 8.200K 2 R 663 678 1 9.020K 7.380K 8.300K 0.0025 110.39 96.531 9.0200 7.3800  

RBR3
Device Loc Side Total Pin Tested Coverage (%) Comment
RBR3 C2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 678 N41678282

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
942 RBR3 8.200K 8.200K 2 R 1 678 663 9.020K 7.380K 8.270K 0.0049 55.480 50.733 9.0200 7.3800  

RL1R1
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R1 C1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 647 L1_LREXT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
884 RL1R1 2.490K 2.490K 2 R 1 647 0 2.739K 2.241K 2.540K 0.0049 16.933 13.596 2.7400 2.2400  

RL1R17
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R17 B1 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 584 CLKREQ__LAN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1020 RL1R17 8.200K 8.200K 2 R 549 584 0 9.020K 7.380K 8.190K 0.0052 52.831 51.991 9.0200 7.3800  

RL1R2
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R2 B1 T 2 2 100.0  

Pin Nail Net Name
1 564 L1_ISOLATE_
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
824 RL1R2 1.000K 1.000K 2 R 2 564 1 1.100K 0.900K 1.020K 0.0005 66.442 55.233 1.1000 0.9000  

RL1R3
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R3 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 564 L1_ISOLATE_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1080 RL1R3 15.00K 15.00K 2 R 1 564 2 16.50K 13.50K 14.61K 0.0090 55.619 41.155 16.500 13.500  

RL1R5
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R5 C1 T 2 2 100.0  

Pin Nail Net Name
1 650 L1_LINK1000__R
2 639 L1_LINK1000_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
779 RL1R5 300.00 300.00 2 R 639 650 0 420.00 180.00 307.37 0.3343 119.65 112.30 420.00 180.00  

RL1R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R6 C1 T 2 2 100.0  

Pin Nail Net Name
1 651 +3VSB_LAN1
2 641 L1_ACTLEDP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
780 RL1R6 300.00 300.00 2 R 651 641 0 420.00 180.00 307.07 0.5821 68.719 64.670 420.00 180.00  

RL1R85
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R85 C1 T 2 2 100.0  

Pin Nail Net Name
1 651 +3VSB_LAN1
2 649 S_WAKE__LAN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1012 RL1R85 8.200K 8.200K 2 R 651 649 0 9.020K 7.380K 7.930K 0.0060 45.297 30.575 9.0200 7.3800  

RD3R109
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R109 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1193 H_D3B_VREFDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
827 RD3R109 1.000K 1.000K 2 R 1 1193 1148 1.100K 0.900K 0.930K 0.0140 2.3880 0.6950 1.1000 0.9000  

RD3R2
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R2 D4 T 2 2 100.0 Parallel RD3R1

Pin Nail Net Name
1 828 H_D3B_VREFCA
2 1148 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
828 RD3R2/R 1.000K 0.500K 2 R 828 1148 1158 0.550K 0.450K 0.470K 0.0097 1.7230 0.7900 0.5500 0.4500  

RD3R21
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R21 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1221 N60799296

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
725 RD3R21 24.90 24.90 2 R 1 1221 0 34.86 14.94 27.03 0.0128 258.54 203.13 34.860 14.940  

RD3R22
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R22 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1203 N60799295

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
726 RD3R22 24.90 24.90 2 R 1 1203 0 34.86 14.94 27.00 0.0093 355.78 280.79 34.860 14.940  

RD3R23
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R23 D4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 798 N60799305

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
727 RD3R23 24.90 24.90 2 R 1 798 0 34.86 14.94 26.99 0.0202 164.57 130.10 34.860 14.940  

RD3R3
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R3 D4 T 2 2 100.0 Parallel RD3R4

Pin Nail Net Name
1 1 GND
2 875 H_D3A_VREFCA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
830 RD3R3/R 1.000K 0.500K 2 R 1 875 1148 0.550K 0.450K 0.460K 0.0057 2.9280 0.5640 0.5500 0.4500  

RD3R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R6 F4 T 2 2 100.0  

Pin Nail Net Name
1 1213 H_D3A_VREFDQ
2 1148 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
832 RD3R6 1.000K 1.000K 2 R 1148 1213 1 1.100K 0.900K 1.080K 0.0055 6.0930 1.2400 1.1000 0.9000  

RD3R7
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R7 F4 T 2 2 100.0  

Pin Nail Net Name
1 1193 H_D3B_VREFDQ
2 1148 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
833 RD3R7 1.000K 1.000K 2 R 1148 1193 1 1.100K 0.900K 1.070K 0.0193 1.7310 0.5640 1.1000 0.9000  

RD3R8
Device Loc Side Total Pin Tested Coverage (%) Comment
RD3R8 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1213 H_D3A_VREFDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
834 RD3R8 1.000K 1.000K 2 R 1 1213 1148 1.100K 0.900K 1.090K 0.0022 15.199 1.6080 1.1000 0.9000  

LAL1
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL1 B1 T 2 2 100.0  

Pin Nail Net Name
1 17 A_LINE_L_L
2 609 A_LINE_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1885 LAL1 75.00 75.00 2 R 17 609 0 105.00 45.00 77.90 0.0232 431.07 389.36 105.00 45.000  

LAL13
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL13 A1 T 2 2 100.0  

Pin Nail Net Name
1 37 A_HPOUT_L_L
2 61 A_HPOUT_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1886 LAL13 75.00 75.00 2 R 37 61 0 105.00 45.00 77.31 0.0391 255.45 235.80 105.00 45.000  

LAL14
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL14 A1 T 2 2 100.0  

Pin Nail Net Name
1 36 A_HPOUT_R_L
2 59 A_HPOUT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1887 LAL14 75.00 75.00 2 R 36 59 0 105.00 45.00 77.18 0.0825 121.24 112.44 105.00 45.000  

LAL15
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL15 A1 T 2 2 100.0  

Pin Nail Net Name
1 7 A_FMIC1_L_L
2 38 A_FMIC1_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1888 LAL15 75.00 75.00 2 R 7 38 0 105.00 45.00 77.30 0.0454 220.37 203.45 105.00 45.000  

LAL16
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL16 A1 T 2 2 100.0  

Pin Nail Net Name
1 19 A_FMIC1_R_L
2 58 A_FMIC1_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1889 LAL16 75.00 75.00 2 R 19 58 0 105.00 45.00 77.25 0.0255 391.98 362.54 105.00 45.000  

LAL2
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL2 B1 T 2 2 100.0  

Pin Nail Net Name
1 613 A_LINE_R_L
2 629 A_LINE_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1890 LAL2 75.00 75.00 2 R 613 629 0 105.00 45.00 77.62 0.0475 210.51 192.14 105.00 45.000  

LAL3
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL3 B1 T 2 2 100.0  

Pin Nail Net Name
1 8 A_LOUT_L_L
2 612 A_LOUT_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1891 LAL3 75.00 75.00 2 R 8 612 0 105.00 45.00 77.50 0.0355 281.33 257.91 105.00 45.000  

LAL4
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL4 B1 T 2 2 100.0  

Pin Nail Net Name
1 6 A_LOUT_R_L
2 627 A_LOUT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1892 LAL4 75.00 75.00 2 R 6 627 0 105.00 45.00 77.73 0.0512 195.32 177.53 105.00 45.000  

LAL5
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL5 B1 T 2 2 100.0  

Pin Nail Net Name
1 20 A_MIC1_L_L
2 619 A_MIC1_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1893 LAL5 75.00 75.00 2 R 20 619 0 105.00 45.00 77.56 0.0449 222.49 203.47 105.00 45.000  

LAL6
Device Loc Side Total Pin Tested Coverage (%) Comment
LAL6 B1 T 2 2 100.0  

Pin Nail Net Name
1 23 A_MIC1_R_L
2 621 A_MIC1_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1894 LAL6 75.00 75.00 2 R 23 621 0 105.00 45.00 77.59 0.0367 272.23 248.72 105.00 45.000  

RAR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR1 A1 T 2 2 100.0  

Pin Nail Net Name
1 628 A_GND
2 51 A_JDREF

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1083 RAR1 20.00K 20.00K 2 R 628 51 0 22.00K 18.00K 19.05K 0.0046 146.43 76.749 22.000 18.000  

RAR10
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR10 A1 T 2 2 100.0  

Pin Nail Net Name
1 60 A_JD_FRONT
2 44 A_SENSE_B

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
748 RAR10 47.00 47.00 2 R 60 44 0 65.80 28.20 48.94 0.0193 324.67 291.12 65.800 28.200  

RAR100
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR100 B1 T 2 2 100.0  

Pin Nail Net Name
1 593 AUDIO_LED_PWM
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
943 RAR100 8.200K 8.200K 2 R 549 593 0 9.020K 7.380K 7.930K 0.0075 36.377 24.270 9.0200 7.3800  

RAR11
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR11 A1 T 2 2 100.0  

Pin Nail Net Name
1 117 A_HD_SDIN0
2 47 A_HD_SDIN0_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
716 RAR11 22.00 22.00 0 R 47 117 0 30.80 13.20 23.54 0.0078 377.49 311.38 30.800 13.200  

RAR2
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR2 B1 T 2 2 100.0  

Pin Nail Net Name
1 26 A_SENSE_A
2 611 A_JD_LOUT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
930 RAR2 5.100K 5.100K 2 R 26 611 0 5.610K 4.590K 5.130K 0.0022 78.809 74.211 5.6100 4.5900  

RAR250
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR250 A1 T 2 2 100.0  

Pin Nail Net Name
1 68 N16996174
2 66 MUTE_POP_EN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
999 RAR250 8.200K 8.200K 2 R 66 68 0 9.020K 7.380K 8.210K 0.0041 66.002 65.500 9.0200 7.3800  

RAR251
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR251 A1 T 2 2 100.0  

Pin Nail Net Name
1 11 A_VREF_MIC1_L_Q
2 20 A_MIC1_L_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
901 RAR251 2.700K 2.700K 2 R 20 11 0 2.970K 2.430K 2.750K 0.0053 16.982 13.654 2.9700 2.4300  

RAR252
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR252 A1 T 2 2 100.0  

Pin Nail Net Name
1 10 A_VREF_MIC1_R_Q
2 23 A_MIC1_R_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
885 RAR252 2.700K 2.700K 2 R 23 10 0 2.970K 2.430K 2.740K 0.0044 20.665 17.825 2.9700 2.4300  

RAR253
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR253 A1 T 2 2 100.0  

Pin Nail Net Name
1 35 A_VREF_FMIC2_L
2 39 A_HPOUT_L_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
886 RAR253 2.700K 2.700K 2 R 39 35 0 2.970K 2.430K 2.740K 0.0029 30.773 26.415 2.9700 2.4300  

RAR254
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR254 A1 T 2 2 100.0  

Pin Nail Net Name
1 34 A_VREF_FMIC2_R
2 40 A_HPOUT_R_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
887 RAR254 2.700K 2.700K 2 R 40 34 0 2.970K 2.430K 2.740K 0.0061 14.876 12.499 2.9700 2.4300  

RAR255
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR255 A1 T 2 2 100.0  

Pin Nail Net Name
1 13 A_VREF_FMIC1_L
2 7 A_FMIC1_L_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
888 RAR255 2.700K 2.700K 2 R 7 13 0 2.970K 2.430K 2.740K 0.0074 12.215 10.575 2.9700 2.4300  

RAR256
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR256 A1 T 2 2 100.0  

Pin Nail Net Name
1 12 A_VREF_FMIC1_R
2 19 A_FMIC1_R_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
904 RAR256 2.700K 2.700K 2 R 19 12 0 2.970K 2.430K 2.750K 0.0044 20.333 16.611 2.9700 2.4300  

RAR257
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR257 A1 T 2 2 100.0  

Pin Nail Net Name
1 628 A_GND
2 64 A_LOUT_L_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
842 RAR257 1.000K 1.000K 2 R 628 64 0 1.100K 0.900K 1.010K 0.0007 48.695 43.769 1.1000 0.9000  

RAR258
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR258 A1 T 2 2 100.0  

Pin Nail Net Name
1 628 A_GND
2 18 A_LOUT_R_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
847 RAR258 1.000K 1.000K 2 R 18 628 0 1.100K 0.900K 1.020K 0.0009 35.196 28.028 1.1000 0.9000  

RAR259
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR259 A1 T 2 2 100.0  

Pin Nail Net Name
1 66 MUTE_POP_EN
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1123 RAR259 100.00K 100.00K 2 R 549 66 1 110.00K 90.00K 100.94K 1.6821 1.9820 1.7960 110.00 90.000  

RAR260
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR260 A1 T 2 2 100.0  

Pin Nail Net Name
1 67 MUTE_POP
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1124 RAR260 100.00K 100.00K 2 R 4 67 1 130.00K 70.00K 99.57K 14.254 0.7020 0.6920 130.00 70.000  

RAR269
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR269 B1 B 2 2 100.0  

Pin Nail Net Name
1 585 N16978758
2 107 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
783 RAR269 300.00 300.00 2 R 107 585 0 420.00 180.00 307.19 0.5423 73.757 69.338 420.00 180.00  

RAR271
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR271 B1 B 2 2 100.0  

Pin Nail Net Name
1 617 N72387148
2 107 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
784 RAR271 300.00 300.00 2 R 107 617 0 420.00 180.00 307.78 0.3117 128.33 120.02 420.00 180.00  

RAR273
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR273 A1 B 2 2 100.0  

Pin Nail Net Name
1 65 N72387164
2 107 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
786 RAR273 300.00 300.00 2 R 107 65 0 420.00 180.00 306.30 0.3589 111.45 105.60 420.00 180.00  

RAR274
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR274 A1 B 2 2 100.0  

Pin Nail Net Name
1 602 N72387179
2 107 +5VSB_DUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
787 RAR274 300.00 300.00 2 R 107 602 0 420.00 180.00 306.28 0.5392 74.181 70.300 420.00 180.00  

RAR3
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR3 B1 T 2 2 100.0  

Pin Nail Net Name
1 26 A_SENSE_A
2 610 A_JD_LINE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1057 RAR3 10.00K 10.00K 2 R 26 610 0 11.00K 9.00K 10.13K 0.0062 53.546 46.690 11.000 9.0000  

RAR4
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR4 B1 T 2 2 100.0  

Pin Nail Net Name
1 26 A_SENSE_A
2 620 A_JD_MIC1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1088 RAR4 20.00K 20.00K 2 R 26 620 0 22.00K 18.00K 20.35K 0.0200 33.269 27.435 22.000 18.000  

RAR8
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR8 A1 T 2 2 100.0  

Pin Nail Net Name
1 56 A_JD_FMIC1
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1082 RAR8 20.00K 20.00K 2 R 628 56 0 22.00K 18.00K 20.27K 0.0214 31.153 26.923 22.000 18.000  

RAR9
Device Loc Side Total Pin Tested Coverage (%) Comment
RAR9 A1 T 2 2 100.0  

Pin Nail Net Name
1 62 A_JD_HPOUT
2 628 A_GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1097 RAR9 39.20K 39.20K 2 R 628 62 0 43.12K 35.28K 35.73K 0.0114 114.57 13.073 43.120 35.280  

RAU2R1
Device Loc Side Total Pin Tested Coverage (%) Comment
RAU2R1 A1 T 2 2 100.0  

Pin Nail Net Name
1 16 AMP_IN_L
2 9 AMP_OUT_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
881 RAU2R1 2.000K 2.000K 2 R 9 16 0 2.200K 1.800K 2.030K 0.0027 24.707 20.891 2.2000 1.8000  

RAU2R2
Device Loc Side Total Pin Tested Coverage (%) Comment
RAU2R2 A1 T 2 2 100.0  

Pin Nail Net Name
1 64 A_LOUT_L_A
2 16 AMP_IN_L

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
845 RAU2R2 1.000K 1.000K 2 R 16 64 0 1.100K 0.900K 1.010K 0.0005 65.939 59.154 1.1000 0.9000  

RAU2R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RAU2R6 A1 T 2 2 100.0  

Pin Nail Net Name
1 18 A_LOUT_R_A
2 24 AMP_IN_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
829 RAU2R6 1.000K 1.000K 2 R 18 24 0 1.100K 0.900K 1.010K 0.0006 53.646 48.254 1.1000 0.9000  

RAU2R7
Device Loc Side Total Pin Tested Coverage (%) Comment
RAU2R7 A1 T 2 2 100.0  

Pin Nail Net Name
1 24 AMP_IN_R
2 15 AMP_OUT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
880 RAU2R7 2.000K 2.000K 2 R 15 24 0 2.200K 1.800K 2.020K 0.0026 25.851 22.779 2.2000 1.8000  

REATXR16
Device Loc Side Total Pin Tested Coverage (%) Comment
REATXR16 C4 T 2 2 100.0  

Pin Nail Net Name
1 794 ATX_PSON__R
2 523 O_PSON__O1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
740 REATXR16 33.00 33.00 0 R 523 794 0 46.20 19.80 35.73 0.0204 215.90 171.22 46.200 19.800  

REATXR216
Device Loc Side Total Pin Tested Coverage (%) Comment
REATXR216 C4 T 2 2 100.0  

Pin Nail Net Name
1 523 O_PSON__O1
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1086 REATXR216 20.00K 20.00K 2 R 797 523 0 22.00K 18.00K 19.83K 0.6320 1.0550 0.9630 22.000 18.000  

RGR129
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR129 E1 T 2 2 100.0  

Pin Nail Net Name
1 1350 H_DVI_TXDN2_C
2 998 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
789 RGR129 470.00 470.00 2 R 998 1350 0 658.00 282.00 475.10 0.1315 476.51 463.58 658.00 282.00  

RGR130
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR130 E1 T 2 2 100.0  

Pin Nail Net Name
1 1351 H_DVI_TXDP2_C
2 998 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
790 RGR130 470.00 470.00 2 R 998 1351 0 658.00 282.00 475.54 0.0181 3468.5 3366.2 658.00 282.00  

RGR131
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR131 E1 T 2 2 100.0  

Pin Nail Net Name
1 1353 H_DVI_TXDN1_C
2 998 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
791 RGR131 470.00 470.00 2 R 998 1353 0 658.00 282.00 478.93 0.1656 378.35 360.38 658.00 282.00  

RGR132
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR132 E1 T 2 2 100.0  

Pin Nail Net Name
1 1352 H_DVI_TXDP1_C
2 998 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
792 RGR132 470.00 470.00 2 R 998 1352 0 658.00 282.00 473.51 0.0636 984.60 966.24 658.00 282.00  

RGR133
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR133 E1 T 2 2 100.0  

Pin Nail Net Name
1 1354 H_DVI_TXDN0_C
2 998 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
794 RGR133 470.00 470.00 2 R 998 1354 0 658.00 282.00 476.64 0.1670 375.17 361.93 658.00 282.00  

RGR134
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR134 E1 T 2 2 100.0  

Pin Nail Net Name
1 1355 H_DVI_TXDP0_C
2 998 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
795 RGR134 470.00 470.00 2 R 998 1355 0 658.00 282.00 474.90 0.2593 241.71 235.42 658.00 282.00  

RGR135
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR135 E1 T 2 2 100.0  

Pin Nail Net Name
1 999 H_DVI_TXCN_C
2 998 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
796 RGR135 470.00 470.00 2 R 998 999 0 658.00 282.00 473.39 0.1848 339.13 333.02 658.00 282.00  

RGR136
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR136 E1 T 2 2 100.0  

Pin Nail Net Name
1 1000 H_DVI_TXCP_C
2 998 N17605037

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
797 RGR136 470.00 470.00 2 R 998 1000 0 658.00 282.00 475.85 0.1827 343.08 332.39 658.00 282.00  

RGR151
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR151 E1 T 2 2 100.0  

Pin Nail Net Name
1 1006 SW_DVI_HPD
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1085 RGR151 20.00K 20.00K 2 R 1 1006 0 22.00K 18.00K 20.31K 0.0250 26.678 22.493 22.000 18.000  

RGR251
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR251 E1 T 2 2 100.0  

Pin Nail Net Name
1 153 S_DVI_HPD
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1135 RGR251 1.000M 1.000M 2 R 2 153 1 1.300M 0.700M 1.000M 0.0006 164.19 161.99 1.3000 0.7000  

RGR69
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR69 E1 T 2 2 100.0  

Pin Nail Net Name
1 1009 SW_DVI_DDC_CLK
2 1005 +5V_DVI_HDMI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
905 RGR69 2.700K 2.700K 2 R 1009 1005 0 2.970K 2.430K 2.740K 0.0071 12.633 10.706 2.9700 2.4300  

RGR70
Device Loc Side Total Pin Tested Coverage (%) Comment
RGR70 E1 T 2 2 100.0  

Pin Nail Net Name
1 1008 SW_DVI_DDC_DATA
2 1005 +5V_DVI_HDMI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
903 RGR70 2.700K 2.700K 2 R 1008 1005 0 2.970K 2.430K 2.750K 0.0068 13.226 10.674 2.9700 2.4300  

RHR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR1 C3 T 2 2 100.0  

Pin Nail Net Name
1 903 H_HDA_SDI_R
2 683 H_HDA_SDI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
733 RHR1 33.00 33.00 2 R 683 903 0 46.20 19.80 35.81 0.0207 212.65 167.35 46.200 19.800  

RHR105
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR105 C2 T 2 2 100.0  

Pin Nail Net Name
1 492 H_CPU_TRIGGER
2 688 H_CPU_TRIGGER_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
714 RHR105 20.00 20.00 0 R 688 492 0 28.00 12.00 21.82 0.0068 389.70 301.17 28.000 12.000  

RHR202
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR202 E2 T 2 2 100.0  

Pin Nail Net Name
1 1279 P_VCORE_VRHOT__R_10
2 426 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
841 RHR202 1.000K 1.000K 2 R 426 1279 0 1.100K 0.900K 1.010K 0.0005 71.365 60.883 1.1000 0.9000  

RHR203
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR203 C2 T 2 2 100.0  

Pin Nail Net Name
1 941 H_THERMTRIP_
2 426 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
843 RHR203 1.000K 1.000K 2 R 426 941 0 1.100K 0.900K 0.970K 0.0007 48.604 36.233 1.1000 0.9000  

RHR208
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR208 E2 T 2 2 100.0  

Pin Nail Net Name
1 1047 H_SVID_ALERT__R
2 1278 H_SVID_ALERT_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
776 RHR208 220.00 220.00 2 R 1278 1047 0 308.00 132.00 224.58 0.3086 95.067 90.115 308.00 132.00  

RHR209
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR209 E2 T 2 2 100.0  

Pin Nail Net Name
1 1278 H_SVID_ALERT_
2 426 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
760 RHR209 56.20 56.20 0 R 426 1278 0 78.68 33.72 58.41 0.0353 212.24 191.41 78.680 33.720  

RHR217
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR217 C2 T 2 2 100.0  

Pin Nail Net Name
1 493 H_PM_DOWN
2 938 H_PM_DOWN_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
715 RHR217 20.00 20.00 0 R 938 493 0 28.00 12.00 21.88 0.0261 102.03 78.037 28.000 12.000  

RHR218
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR218 E2 T 2 2 100.0  

Pin Nail Net Name
1 1279 P_VCORE_VRHOT__R_10
2 1045 H_PROCHOT__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
809 RHR218 499.00 499.00 2 R 1279 1045 0 698.60 299.40 505.74 0.1346 494.29 477.60 698.60 299.40  

RHR52
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR52 D3 T 2 2 100.0  

Pin Nail Net Name
1 946 VCCIO
2 910 H_PEG_RCOMP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
728 RHR52 24.90 24.90 2 R 946 910 0 34.86 14.94 27.14 0.0075 441.41 342.34 34.860 14.940  

RHR61
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR61 D3 T 2 2 100.0  

Pin Nail Net Name
1 909 H_DP_RCOMP
2 946 VCCIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
729 RHR61 24.90 24.90 2 R 946 909 0 34.86 14.94 27.19 0.0178 186.43 143.55 34.860 14.940  

RHR90
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR90 D3 T 2 2 100.0  

Pin Nail Net Name
1 911 H_CFG_RCOMP
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
749 RHR90 49.90 49.90 2 R 1 911 0 69.86 29.94 51.90 0.0199 334.35 300.82 69.860 29.940  

RHR96
Device Loc Side Total Pin Tested Coverage (%) Comment
RHR96 D2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 925 H_CFG4

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
818 RHR96 1.000K 1.000K 2 R 1 925 0 1.100K 0.900K 1.010K 0.0009 37.177 32.780 1.1000 0.9000  

RHTR1
Device Loc Side Total Pin Tested Coverage (%) Comment
RHTR1 D3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 70 H_TR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1122 RHTR1 10.00K 10.00K 2 R 1 70 615 13.00K 7.00K 7.96K 0.0305 32.785 10.473 13.000 7.0000  

RO1R1
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R1 B1 T 2 2 100.0  

Pin Nail Net Name
1 130 O_RSMRST_
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1047 RO1R1 8.200K 8.200K 2 R 549 130 0 9.020K 7.380K 8.120K 0.0057 48.024 43.156 9.0200 7.3800  

RO1R10
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R10 B1 T 2 2 100.0  

Pin Nail Net Name
1 129 S_SLP_S4_
2 594 O_SLP_S4__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
785 RO1R10 300.00 300.00 2 R 129 594 0 420.00 180.00 308.05 0.4198 95.286 88.893 420.00 180.00  

RO1R12
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R12 B1 T 2 2 100.0  

Pin Nail Net Name
1 524 O_PWROK
2 586 O_PWROK_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
737 RO1R12 33.00 33.00 2 R 524 586 0 46.20 19.80 35.80 0.0239 184.19 145.12 46.200 19.800  

RO1R13
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R13 B1 T 2 2 100.0  

Pin Nail Net Name
1 592 O_RSTCON__P_R
2 343 O_RSTCON__P

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
819 RO1R13 1.000K 1.000K 2 R 343 592 0 1.100K 0.900K 1.010K 0.0007 49.254 43.222 1.1000 0.9000  

RO1R14
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R14 B1 T 2 2 100.0  

Pin Nail Net Name
1 579 O_PWRBTN__R
2 569 PWRBTN_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
862 RO1R14 1.000K 1.000K 2 R 569 579 0 1.100K 0.900K 1.010K 0.0008 39.914 35.364 1.1000 0.9000  

RO1R18
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R18 B1 T 2 2 100.0  

Pin Nail Net Name
1 154 O_IOPWRBTN_
2 578 O_IOPWRBTN__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
734 RO1R18 33.00 33.00 2 R 578 154 0 46.20 19.80 35.90 0.0242 181.55 141.62 46.200 19.800  

RO1R19
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R19 B1 T 2 2 100.0  

Pin Nail Net Name
1 566 O_PME_
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
950 RO1R19 8.200K 8.200K 2 R 549 566 0 9.020K 7.380K 8.170K 0.0055 49.610 47.602 9.0200 7.3800  

RO1R198
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R198 B1 T 2 2 100.0  

Pin Nail Net Name
1 544 O_X1_RST_
2 582 O_X1_RST__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
735 RO1R198 33.00 33.00 2 R 544 582 0 46.20 19.80 35.62 0.0201 218.44 175.08 46.200 19.800  

RO1R199
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R199 B1 T 2 2 100.0  

Pin Nail Net Name
1 551 O_X16_RST_
2 583 O_X16_RST__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
736 RO1R199 33.00 33.00 2 R 551 583 0 46.20 19.80 35.63 0.0107 409.48 327.82 46.200 19.800  

RO1R2
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R2 B1 T 2 2 100.0  

Pin Nail Net Name
1 578 O_IOPWRBTN__R
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
858 RO1R2 1.000K 1.000K 2 R 549 578 0 1.100K 0.900K 1.010K 0.0007 48.596 43.410 1.1000 0.9000  

RO1R21
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R21 B1 T 2 2 100.0  

Pin Nail Net Name
1 603 O_PLED
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1035 RO1R21 8.200K 8.200K 2 R 549 603 0 9.020K 7.380K 8.050K 0.0057 48.229 39.465 9.0200 7.3800  

RO1R23
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R23 B1 T 2 2 100.0 U

Pin Nail Net Name
1 595 O1_P46
2 71 +3V_BAT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1138 RO1R23/U 2.000M 2.000M 2 R 71 595 115 2.600M 0.800M 0.860M 0.3010 0.8860 0.1500 2.6000 1.0000  

RO1R24
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R24 B1 T 2 2 100.0  

Pin Nail Net Name
1 608 O_5V_IN_2
2 71 +3V_BAT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1139 RO1R24 2.000M 2.000M 2 R 71 608 0 2.600M 1.400M 1.920M 0.0412 4.8580 4.2380 2.6000 1.4000  

RO1R25
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R25 B1 T 2 2 100.0  

Pin Nail Net Name
1 72 O_KBRST_
2 572 O_KBRST__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
781 RO1R25 300.00 300.00 2 R 72 572 0 420.00 180.00 306.80 0.3560 112.35 105.98 420.00 180.00  

RO1R3
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R3 B1 T 2 2 100.0  

Pin Nail Net Name
1 133 O_RSTCON_
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1010 RO1R3 8.200K 8.200K 2 R 2 133 0 9.020K 7.380K 7.950K 0.0044 62.618 43.211 9.0200 7.3800  

RO1R30
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R30 B1 T 2 2 100.0  

Pin Nail Net Name
1 604 O_VCORE_IN
2 563 O_VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
820 RO1R30 1.000K 1.000K 2 R 563 604 1 1.100K 0.900K 1.060K 0.0012 28.266 9.9280 1.1000 0.9000  

RO1R31
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R31 B1 T 2 2 100.0  

Pin Nail Net Name
1 604 O_VCORE_IN
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
821 RO1R31 1.000K 1.000K 2 R 1 604 563 1.100K 0.900K 1.080K 0.0024 13.810 3.1560 1.1000 0.9000  

RO1R32
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R32 B1 T 2 2 100.0  

Pin Nail Net Name
1 607 O_12V_IN_1
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1078 RO1R32 11.00K 11.00K 2 R 4 607 1 12.10K 9.90K 11.04K 0.0102 36.029 34.688 12.100 9.9000  

RO1R33
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R33 B1 T 2 2 100.0  

Pin Nail Net Name
1 607 O_12V_IN_1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
823 RO1R33 1.000K 1.000K 2 R 1 607 797 1.100K 0.900K 0.940K 0.0010 32.213 13.271 1.1000 0.9000  

RO1R34
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R34 B1 T 2 2 100.0  

Pin Nail Net Name
1 606 O_5V_IN_1
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1102 RO1R34 40.20K 40.20K 2 R 3 606 1 44.22K 36.18K 40.47K 0.0123 109.06 101.71 44.220 36.180  

RO1R35
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R35 B1 T 2 2 100.0  

Pin Nail Net Name
1 606 O_5V_IN_1
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1067 RO1R35 10.00K 10.00K 2 R 1 606 3 11.00K 9.00K 10.19K 0.0081 41.281 33.516 11.000 9.0000  

RO1R4
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R4 B1 T 2 2 100.0  

Pin Nail Net Name
1 586 O_PWROK_R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
825 RO1R4 1.000K 1.000K 2 R 2 586 0 1.100K 0.900K 1.010K 0.0004 89.223 81.630 1.1000 0.9000  

RO1R40
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R40 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 556 O_COM1_RTS1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
813 RO1R40 680.00 680.00 2 R 1 556 0 952.00 408.00 687.57 0.1875 483.68 470.23 952.00 408.00  

RO1R43
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R43 B1 T 2 2 100.0  

Pin Nail Net Name
1 558 O_COM1_DTR1_
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
814 RO1R43 680.00 680.00 2 R 2 558 0 952.00 408.00 687.81 0.3044 297.88 289.33 952.00 408.00  

RO1R44
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R44 B1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 557 O_COM1_TXD1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
815 RO1R44 680.00 680.00 2 R 1 557 0 952.00 408.00 687.15 0.1822 497.52 484.45 952.00 408.00  

RO1R6
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R6 B1 T 2 2 100.0  

Pin Nail Net Name
1 569 PWRBTN_
2 399 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1022 RO1R6 8.200K 8.200K 2 R 399 569 0 9.020K 7.380K 8.220K 0.0078 35.225 34.389 9.0200 7.3800  

RO1R7
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R7 B1 T 2 2 100.0  

Pin Nail Net Name
1 343 O_RSTCON__P
2 399 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1031 RO1R7 8.200K 8.200K 2 R 399 343 0 9.020K 7.380K 8.040K 0.0343 7.9740 6.3900 9.0200 7.3800  

RO1R97
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R97 B1 T 2 2 100.0  

Pin Nail Net Name
1 427 S_SLP_S3_
2 588 O1_PME_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
782 RO1R97 300.00 300.00 2 R 427 588 0 420.00 180.00 308.69 0.5384 74.296 68.914 420.00 180.00  

ROR202
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR202 A4 T 2 2 100.0  

Pin Nail Net Name
1 569 PWRBTN_
2 346 PWRBTN__PANEL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
738 ROR202 33.00 33.00 0 R 569 346 0 46.20 19.80 35.89 0.0164 268.40 209.70 46.200 19.800  

ROR204
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR204 A4 T 2 2 100.0  

Pin Nail Net Name
1 343 O_RSTCON__P
2 347 O_RSTCON__PR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
739 ROR204 33.00 33.00 2 R 343 347 0 46.20 19.80 35.70 0.0278 158.27 125.95 46.200 19.800  

ROR217
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR217 B1 T 2 2 100.0  

Pin Nail Net Name
1 70 H_TR
2 615 O_VREF_SIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1058 ROR217 10.00K 10.00K 2 R 615 70 1 11.00K 9.00K 10.12K 0.0279 11.965 10.525 11.000 9.0000  

ROR218
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR218 B1 T 2 2 100.0  

Pin Nail Net Name
1 576 O_TR_MB
2 615 O_VREF_SIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1061 ROR218 10.00K 10.00K 2 R 615 576 1 11.00K 9.00K 10.17K 0.0367 9.0940 7.5040 11.000 9.0000  

ROR300
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR300 F2 T 2 2 100.0  

Pin Nail Net Name
1 1304 O_CPUFANIN_R
2 590 O_CPUFANIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
889 ROR300 2.700K 2.700K 2 R 1304 590 0 2.970K 2.430K 2.740K 0.0059 15.233 12.942 2.9700 2.4300  

ROR301
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR301 F3 T 2 2 100.0  

Pin Nail Net Name
1 1304 O_CPUFANIN_R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
891 ROR301 2.700K 2.700K 2 R 2 1304 0 2.970K 2.430K 2.740K 0.0116 7.7420 6.6190 2.9700 2.4300  

ROR302
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR302 F1 T 2 2 100.0  

Pin Nail Net Name
1 1338 O_CPUFAN_PWM_B
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
892 ROR302 2.700K 2.700K 2 R 2 1338 0 2.970K 2.430K 2.740K 0.0088 10.246 8.8070 2.9700 2.4300  

ROR303
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR303 F2 T 2 2 100.0  

Pin Nail Net Name
1 1305 O_CPUFAN_PWM_Q
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
893 ROR303 2.700K 2.700K 2 R 3 1305 0 2.970K 2.430K 2.740K 0.0055 16.222 13.809 2.9700 2.4300  

ROR310
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR310 C1 T 2 2 100.0  

Pin Nail Net Name
1 669 O_CHAFANIN1_R
2 591 O_CHAFANIN1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
894 ROR310 2.700K 2.700K 2 R 669 591 0 2.970K 2.430K 2.750K 0.0054 16.763 13.880 2.9700 2.4300  

ROR311
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR311 C1 T 2 2 100.0  

Pin Nail Net Name
1 669 O_CHAFANIN1_R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
895 ROR311 2.700K 2.700K 2 R 2 669 0 2.970K 2.430K 2.720K 0.0059 15.317 14.089 2.9700 2.4300  

ROR312
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR312 C2 T 2 2 100.0  

Pin Nail Net Name
1 674 O_CHAFAN_PWM_B
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
896 ROR312 2.700K 2.700K 2 R 2 674 0 2.970K 2.430K 2.740K 0.0066 13.687 11.774 2.9700 2.4300  

ROR313
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR313 C1 T 2 2 100.0  

Pin Nail Net Name
1 668 O_CHAFAN_PWM_Q
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
897 ROR313 2.700K 2.700K 2 R 3 668 0 2.970K 2.430K 2.740K 0.0075 11.998 10.200 2.9700 2.4300  

ROR402
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR402 F1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 658 O_KB_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
910 ROR402 4.700K 4.700K 2 R 107 658 0 5.170K 4.230K 4.720K 0.0022 70.768 67.443 5.1700 4.2300  

ROR403
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR403 F1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 561 O_KB_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
911 ROR403 4.700K 4.700K 2 R 107 561 0 5.170K 4.230K 4.670K 0.0012 132.56 123.61 5.1700 4.2300  

ROR404
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR404 B1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 567 O_MS_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
912 ROR404 4.700K 4.700K 2 R 107 567 0 5.170K 4.230K 4.720K 0.0014 111.54 107.05 5.1700 4.2300  

ROR405
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR405 B1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 568 O_MS_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
913 ROR405 4.700K 4.700K 2 R 107 568 0 5.170K 4.230K 4.710K 0.0021 74.942 73.303 5.1700 4.2300  

ROR406
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR406 F1 T 2 2 100.0  

Pin Nail Net Name
1 1344 O_KB_DATA_R
2 658 O_KB_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
741 ROR406 33.00 33.00 2 R 1344 658 0 46.20 19.80 36.26 0.0280 157.26 118.45 46.200 19.800  

ROR407
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR407 F1 T 2 2 100.0  

Pin Nail Net Name
1 1340 O_KB_CLK_R
2 561 O_KB_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
742 ROR407 33.00 33.00 0 R 1340 561 0 46.20 19.80 35.68 0.0260 169.28 134.90 46.200 19.800  

ROR760
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR760 B2 T 2 2 100.0  

Pin Nail Net Name
1 532 N16715606
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
743 ROR760 33.00 33.00 0 R 549 532 0 46.20 19.80 34.53 0.0093 470.93 416.31 46.200 19.800  

ROR761
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR761 B2 T 2 2 100.0  

Pin Nail Net Name
1 533 O_DEEP_S5_12V
2 534 O_DEEP_S5_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
846 ROR761 1.000K 1.000K 2 R 534 533 0 1.100K 0.900K 1.010K 0.0004 91.048 79.658 1.1000 0.9000  

ROR762
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR762 B2 T 2 2 100.0  

Pin Nail Net Name
1 411 O_DEEP_S5
2 534 O_DEEP_S5_C

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
931 ROR762 5.600K 5.600K 2 R 411 534 532 6.160K 5.040K 5.670K 0.0087 21.406 18.581 6.1600 5.0400  

ROR763
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR763 B1 T 2 2 100.0  

Pin Nail Net Name
1 411 O_DEEP_S5
2 399 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
898 ROR763 2.700K 2.700K 2 R 399 411 534 2.970K 2.430K 2.740K 0.0056 16.102 13.618 2.9700 2.4300  

ROR766
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR766 A4 T 2 2 100.0  

Pin Nail Net Name
1 333 SPKO
2 332 SPKO-_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
744 ROR766 33.00 33.00 2 R 333 332 0 46.20 19.80 35.77 0.0287 153.47 121.22 46.200 19.800  

ROR767
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR767 A4 T 2 2 100.0  

Pin Nail Net Name
1 322 +5V_SPKO
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
761 ROR767 75.00 75.00 2 R 3 322 0 105.00 45.00 77.54 0.0362 276.34 252.98 105.00 45.000  

ROR769
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR769 A4 T 2 2 100.0  

Pin Nail Net Name
1 603 O_PLED
2 337 O_PLED_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
952 ROR769 8.200K 8.200K 2 R 337 603 0 9.020K 7.380K 8.180K 0.0054 50.763 49.362 9.0200 7.3800  

ROR770
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR770 A4 T 2 2 100.0  

Pin Nail Net Name
1 316 S_SPKR
2 336 S_SPKR_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
958 ROR770 8.200K 8.200K 2 R 336 316 0 9.020K 7.380K 8.280K 0.0061 44.889 40.495 9.0200 7.3800  

ROR771
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR771 A4 T 2 2 100.0  

Pin Nail Net Name
1 335 PLED+
2 1178 +5VDUAL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
805 ROR771 499.00 499.00 2 R 1178 335 0 698.60 299.40 504.75 0.2026 328.37 318.90 698.60 299.40  

ROR772
Device Loc Side Total Pin Tested Coverage (%) Comment
ROR772 A4 T 2 2 100.0  

Pin Nail Net Name
1 334 HDLED+
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
806 ROR772 499.00 499.00 2 R 3 334 0 698.60 299.40 505.52 0.0843 788.79 763.02 698.60 299.40  

ROTR1
Device Loc Side Total Pin Tested Coverage (%) Comment
ROTR1 A4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 576 O_TR_MB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1126 ROTR1 10.00K 10.00K 2 R 576 1 615 13.00K 7.00K 8.55K 0.0294 34.026 17.569 13.000 7.0000  

RPR101
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR101 F3 T 2 2 100.0  

Pin Nail Net Name
1 1246 P_VCORE_IOUT_10
2 1248 P_VCORE_IOUT_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
874 RPR101 1.500K 1.500K 2 R 1248 1246 0 1.650K 1.350K 1.520K 0.0017 30.074 25.145 1.6500 1.3500  

RPR103
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR103 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1292 P_GT_PWM1A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1125 RPR103 100.00K 100.00K 2 R 1233 1292 0 110.00K 90.00K 98.68K 0.0862 38.671 33.553 110.00 90.000  

RPR104
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR104 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1246 P_VCORE_IOUT_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1089 RPR104 22.00K 22.00K 2 R 1233 1246 0 24.20K 19.80K 21.90K 0.0280 26.229 25.073 24.200 19.800  

RPR105
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR105 F3 T 2 2 100.0  

Pin Nail Net Name
1 1253 P_VCORE_VRMP_10
2 1339 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
855 RPR105 1.000K 1.000K 2 R 1339 1253 0 1.100K 0.900K 1.010K 0.0005 62.751 54.752 1.1000 0.9000  

RPR106
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR106 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1238 P_GT_IOUTA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1090 RPR106 24.30K 24.30K 2 R 1233 1238 0 26.73K 21.87K 24.63K 0.0226 35.834 30.910 26.730 21.870  

RPR107
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR107 F3 T 2 2 100.0 Parallel RHR210

Pin Nail Net Name
1 1273 H_SVID_DATA
2 426 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
765 RPR107/RHR210 100.00 50.00 0 R 426 1273 0 70.00 30.00 52.08 0.0180 370.31 331.73 70.000 30.000  

RPR109
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR109 F3 T 2 2 100.0  

Pin Nail Net Name
1 1050 H_SVID_CLK
2 426 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
747 RPR109 45.30 45.30 2 R 426 1050 0 63.42 27.18 48.65 0.0280 215.75 175.91 63.420 27.180  

RPR111
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR111 F3 T 2 2 100.0  

Pin Nail Net Name
1 1302 P_GT_PHASE1_10
2 1259 P_GT_CSP1A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
936 RPR111 6.800K 6.800K 2 R 1259 1302 0 7.480K 6.120K 6.790K 0.0280 8.1050 8.0040 7.4800 6.1200  

RPR112
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR112 F3 T 2 2 100.0  

Pin Nail Net Name
1 1264 P_GT_CSP2A_10
2 1321 P_GT_PHASE2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
937 RPR112 6.800K 6.800K 2 R 1321 1264 0 7.480K 6.120K 6.730K 0.0176 12.843 11.455 7.4800 6.1200  

RPR113
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR113 F3 T 2 2 100.0 Parallel RPR119

Pin Nail Net Name
1 1260 P_GT_CSSUMA_10
2 1321 P_GT_PHASE2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1114 RPR113/R 90.90K 45.45K 2 R 1321 1260 0 50.00K 38.63K 40.88K 0.0085 221.69 87.576 50.000 38.630  

RPR117
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR117 F3 T 2 2 100.0  

Pin Nail Net Name
1 1266 P_VCORE_CSP1_10
2 1319 P_VCORE_PHASE1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
938 RPR117 6.800K 6.800K 2 R 1319 1266 0 7.480K 6.120K 6.690K 0.0229 9.9090 8.3350 7.4800 6.1200  

RPR118
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR118 F3 T 2 2 100.0  

Pin Nail Net Name
1 1267 P_VCORE_CSP2_10
2 1284 P_VCORE_PHASE2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
939 RPR118 6.800K 6.800K 2 R 1284 1267 0 7.480K 6.120K 6.720K 0.0201 11.271 9.8730 7.4800 6.1200  

RPR122
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR122 F3 T 2 2 100.0  

Pin Nail Net Name
1 1271 P_VCORE_ILIM_10
2 1317 P_VCORE_CSCOMP_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1096 RPR122 37.40K 37.40K 2 R 1317 1271 0 41.14K 33.66K 37.78K 0.0067 184.75 165.80 41.140 33.660  

RPR123
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR123 F3 T 2 2 100.0  

Pin Nail Net Name
1 1258 P_GT_ILIMA_10
2 1289 P_GT_CSCOMPA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1104 RPR123 40.20K 40.20K 2 R 1289 1258 0 44.22K 36.18K 40.16K 0.0099 135.86 134.36 44.220 36.180  

RPR125
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR125 F3 T 2 2 100.0  

Pin Nail Net Name
1 1270 P_VCORE_CSP3_10
2 1042 P_VCORE_PHASE3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
940 RPR125 6.800K 6.800K 2 R 1042 1270 0 7.480K 6.120K 6.710K 0.0043 53.038 45.642 7.4800 6.1200  

RPR127
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR127 F3 T 2 2 100.0 Parallel RPR115

Pin Nail Net Name
1 1283 P_VCORE_CSSUM_10
2 1042 P_VCORE_PHASE3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1110 RPR127/R 90.90K 22.73K 0 R 1283 1042 0 25.00K 20.46K 20.98K 0.0194 39.148 9.0140 25.000 20.460  

RPR128
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR128 E3 T 2 2 100.0  

Pin Nail Net Name
1 1051 H_VSS_SENSE
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
767 RPR128 100.00 100.00 2 R 1 1051 0 140.00 60.00 102.92 0.0768 173.62 160.96 140.00 60.000  

RPR129
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR129 F3 T 2 2 100.0  

Pin Nail Net Name
1 1247 P_VCORE_VSN_10
2 1051 H_VSS_SENSE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
875 RPR129 1.500K 1.500K 2 R 1051 1247 0 1.650K 1.350K 1.520K 0.0009 54.441 47.465 1.6500 1.3500  

RPR130
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR130 F3 T 2 2 100.0  

Pin Nail Net Name
1 1263 P_GT_TMA_10
2 1294 P_GT_TMA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
768 RPR130 100.00 100.00 2 R 1263 1294 0 140.00 60.00 101.79 0.0996 133.89 127.90 140.00 60.000  

RPR132
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR132 F3 T 2 2 100.0  

Pin Nail Net Name
1 1300 P_GT_CSPA_R_10
2 1260 P_GT_CSSUMA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1133 RPR132 316.00K 316.00K 2 R 1260 1300 1289 347.60K 284.40K 333.39K 1.0919 9.6470 4.3380 347.60 284.40  

RPR133
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR133 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1265 P_VCORE_TM_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
811 RPR133 665.00 665.00 2 R 1 1265 1315 931.00 399.00 675.31 0.3754 236.18 227.02 931.00 399.00  

RPR134
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR134 F3 T 2 2 100.0  

Pin Nail Net Name
1 1314 P_VCORE_CSP_R_10
2 1283 P_VCORE_CSSUM_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1132 RPR134 196.00K 196.00K 2 R 1283 1314 1317 215.60K 176.40K 197.51K 0.3459 18.889 17.431 215.60 176.40  

RPR135
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR135 E2 T 2 2 100.0  

Pin Nail Net Name
1 1044 H_VCC_SENSE
2 948 VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
770 RPR135 100.00 100.00 2 R 948 1044 0 140.00 60.00 102.99 0.0485 274.78 254.25 140.00 60.000  

RPR137
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR137 E3 T 2 2 100.0  

Pin Nail Net Name
1 1061 H_GT_VSS_SENSE
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
771 RPR137 100.00 100.00 2 R 1 1061 0 140.00 60.00 102.60 0.0954 139.74 130.66 140.00 60.000  

RPR138
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR138 F3 T 2 2 100.0  

Pin Nail Net Name
1 1046 H_GT_VCC_SENSE
2 1043 VCCGT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
772 RPR138 100.00 100.00 2 R 1043 1046 0 140.00 60.00 103.24 0.0307 434.90 399.70 140.00 60.000  

RPR139
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR139 F3 T 2 2 100.0  

Pin Nail Net Name
1 1245 P_GT_VSNA_10
2 1061 H_GT_VSS_SENSE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
876 RPR139 1.500K 1.500K 2 R 1061 1245 0 1.650K 1.350K 1.530K 0.0008 64.382 52.135 1.6500 1.3500  

RPR140
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR140 F3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1263 P_GT_TMA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
812 RPR140 665.00 665.00 2 R 1 1263 1294 931.00 399.00 675.79 0.4986 177.83 170.61 931.00 399.00  

RPR141
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR141 F3 T 2 2 100.0  

Pin Nail Net Name
1 1265 P_VCORE_TM_10
2 1315 P_VCORE_TM_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
773 RPR141 100.00 100.00 2 R 1265 1315 0 140.00 60.00 101.71 0.0639 208.66 199.76 140.00 60.000  

RPR143
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR143 F3 T 2 2 100.0  

Pin Nail Net Name
1 1281 P_VCORE_CSP4_10
2 1282 P_VCORE_PHASE4_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
941 RPR143 6.800K 6.800K 2 R 1282 1281 0 7.480K 6.120K 6.760K 0.0222 10.207 9.6440 7.4800 6.1200  

RPR146
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR146 F3 T 2 2 100.0  

Pin Nail Net Name
1 1256 P_GT_DIFFA_10
2 1244 P_GT_FBA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
861 RPR146 1.000K 1.000K 2 R 1244 1256 0 1.100K 0.900K 1.010K 0.0007 49.054 42.321 1.1000 0.9000  

RPR147
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR147 F3 T 2 2 100.0  

Pin Nail Net Name
1 1256 P_GT_DIFFA_10
2 1242 P_GT_DIFFA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
753 RPR147 49.90 49.90 2 R 1242 1256 0 69.86 29.94 52.35 0.0284 234.25 205.47 69.860 29.940  

RPR148
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR148 F3 T 2 2 100.0  

Pin Nail Net Name
1 1244 P_GT_FBA_10
2 1243 P_GT_FBA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
934 RPR148 6.650K 6.650K 2 R 1244 1243 0 7.315K 5.985K 6.720K 0.0048 46.345 41.673 7.3200 5.9900  

RPR149
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR149 F3 T 2 2 100.0  

Pin Nail Net Name
1 1293 P_GT_BOOT_R
2 1262 P_GT_PWM2A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1060 RPR149 10.00K 10.00K 2 R 1293 1262 0 11.00K 9.00K 10.13K 0.0054 61.611 53.436 11.000 9.0000  

RPR150
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR150 F3 T 2 2 100.0  

Pin Nail Net Name
1 1285 P_VCORE_BOOT_R
2 1041 P_VCORE_PWM2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1064 RPR150 10.00K 10.00K 2 R 1285 1041 0 11.00K 9.00K 10.10K 0.0064 52.326 46.950 11.000 9.0000  

RPR153
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR153 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1039 P_VCORE_PWM4_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1066 RPR153 10.00K 10.00K 2 R 1233 1039 0 11.00K 9.00K 10.09K 0.0031 107.77 97.886 11.000 9.0000  

RPR154
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR154 F3 T 2 2 100.0  

Pin Nail Net Name
1 1276 P_VCORE_FB_10
2 1277 P_VCORE_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
935 RPR154 6.650K 6.650K 2 R 1276 1277 0 7.315K 5.985K 6.710K 0.0036 62.014 56.885 7.3200 5.9900  

RPR155
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR155 F3 T 2 2 100.0  

Pin Nail Net Name
1 1272 P_VCORE_DIFF_10
2 1276 P_VCORE_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
866 RPR155 1.000K 1.000K 2 R 1276 1272 0 1.100K 0.900K 1.010K 0.0009 38.328 33.494 1.1000 0.9000  

RPR156
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR156 F3 T 2 2 100.0  

Pin Nail Net Name
1 1272 P_VCORE_DIFF_10
2 1274 P_VCORE_DIFF_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
754 RPR156 49.90 49.90 2 R 1274 1272 0 69.86 29.94 52.19 0.0184 361.47 319.92 69.860 29.940  

RPR157
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR157 F2 T 2 2 100.0  

Pin Nail Net Name
1 1331 P_VCORE_PHASE1_20
2 1328 P_VCORE_R_HG1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1024 RPR157 8.200K 8.200K 2 R 1331 1328 1 9.020K 7.380K 8.420K 0.0590 4.6330 3.3780 9.0200 7.3800  

RPR158
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR158 E2 T 2 2 100.0 Parallel QPQ121

Pin Nail Net Name
1 1024 P_VCORE_PHASE2_20
2 1017 P_VCORE_R_HG2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1026 RPR158/Q 8.200K 8.200K 2 R 1024 1017 1 9.020K 6.560K 7.540K 0.0155 26.384 20.976 9.0200 6.5600  

RPR159
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR159 E2 T 2 2 100.0 Parallel QPQ131

Pin Nail Net Name
1 1023 P_VCORE_PHASE3_20
2 1020 P_VCORE_R_HG3_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1027 RPR159/Q 8.200K 8.200K 2 R 1023 1020 1 9.020K 6.560K 7.160K 0.0056 72.943 35.613 9.0200 6.5600  

RPR161
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR161 D2 T 2 2 100.0 Parallel QPQ141

Pin Nail Net Name
1 949 P_VCORE_PHASE4_20
2 960 P_VCORE_R_HG4_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1030 RPR161/Q 8.200K 8.200K 2 R 949 960 1 9.020K 6.560K 7.070K 0.0050 82.052 34.187 9.0200 6.5600  

RPR163
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR163 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1040 P_VCORE_PWM3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1131 RPR163 147.00K 147.00K 2 R 1233 1040 0 161.70K 132.30K 147.39K 0.1107 44.252 43.074 161.70 132.30  

RPR164
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR164 E2 T 2 2 100.0  

Pin Nail Net Name
1 1330 P_VCORE_DRON_10
2 1037 P_OD_2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
756 RPR164 49.90 49.90 2 R 1330 1037 0 69.86 29.94 52.26 0.0326 203.99 179.91 69.860 29.940  

RPR168
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR168 E2 T 2 2 100.0  

Pin Nail Net Name
1 1330 P_VCORE_DRON_10
2 1027 P_OD_3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
757 RPR168 49.90 49.90 2 R 1330 1027 0 69.86 29.94 52.41 0.0289 230.52 201.56 69.860 29.940  

RPR169
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR169 F2 T 2 2 100.0  

Pin Nail Net Name
1 1330 P_VCORE_DRON_10
2 1334 P_OD_1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
758 RPR169 49.90 49.90 2 R 1330 1334 0 69.86 29.94 52.32 0.0367 181.19 159.24 69.860 29.940  

RPR172
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR172 E2 T 2 2 100.0  

Pin Nail Net Name
1 1330 P_VCORE_DRON_10
2 1030 P_OD_4_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
750 RPR172 49.90 49.90 2 R 1330 1030 0 69.86 29.94 52.44 0.0265 251.15 219.17 69.860 29.940  

RPR186
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR186 F3 T 2 2 100.0  

Pin Nail Net Name
1 1050 H_SVID_CLK
2 1251 P_SVID_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
755 RPR186 49.90 49.90 0 R 1050 1251 0 69.86 29.94 52.06 0.0367 181.33 161.69 69.860 29.940  

RPR187
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR187 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1235 P_VRM_PGD_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
902 RPR187 2.700K 2.700K 2 R 1233 1235 3 2.970K 2.430K 2.750K 0.0045 19.940 16.380 2.9700 2.4300  

RPR189
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR189 F3 T 2 2 100.0  

Pin Nail Net Name
1 1235 P_VRM_PGD_10
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1018 RPR189 8.200K 8.200K 2 R 3 1235 1 9.020K 7.380K 8.280K 0.0043 64.184 57.896 9.0200 7.3800  

RPR195
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR195 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1326 P_VCORE_PWM1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1054 RPR195 10.00K 10.00K 2 R 1233 1326 0 11.00K 9.00K 10.13K 0.0070 47.501 41.464 11.000 9.0000  

RPR197
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR197 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1285 P_VCORE_BOOT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1108 RPR197 49.90K 49.90K 2 R 1233 1285 0 54.89K 44.91K 49.77K 0.0143 116.12 113.07 54.890 44.910  

RPR198
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR198 F3 T 2 2 100.0  

Pin Nail Net Name
1 1233 DGND
2 1293 P_GT_BOOT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1107 RPR198 49.90K 49.90K 2 R 1233 1293 0 54.89K 44.91K 47.23K 0.0270 61.496 28.590 54.890 44.910  

RPR201
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR201 F3 T 2 2 100.0  

Pin Nail Net Name
1 1308 P_GT_PHASE1_20
2 1296 P_GT_R_HG1_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
980 RPR201 8.200K 8.200K 2 R 1308 1296 1 9.020K 7.380K 7.540K 0.0175 15.631 3.0240 9.0200 7.3800  

RPR202
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR202 F2 T 2 2 100.0  

Pin Nail Net Name
1 1323 P_GT_PHASE2_20
2 1316 P_GT_R_HG2_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1041 RPR202 8.200K 8.200K 2 R 1323 1316 1 9.020K 6.970K 7.220K 0.0121 28.323 6.9840 9.0200 6.9700  

RPR207
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR207 F3 T 2 2 100.0  

Pin Nail Net Name
1 1330 P_VCORE_DRON_10
2 1298 P_GT_OD_1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
751 RPR207 49.90 49.90 2 R 1330 1298 0 69.86 29.94 52.24 0.0162 410.46 362.37 69.860 29.940  

RPR210
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR210 F2 T 2 2 100.0  

Pin Nail Net Name
1 1330 P_VCORE_DRON_10
2 1309 P_GT_OD_2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
752 RPR210 49.90 49.90 2 R 1330 1309 0 69.86 29.94 52.44 0.0196 339.26 296.07 69.860 29.940  

RPR224
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR224 F3 T 2 2 100.0  

Pin Nail Net Name
1 1255 P_GT_IOUTA_R_10
2 1238 P_GT_IOUTA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
816 RPR224 715.00 715.00 2 R 1238 1255 0 1001.00 429.00 724.94 0.3552 268.39 259.06 1001.0 429.00  

RPR225
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR225 F3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 1236 P_VCORE_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
836 RPR225 1.000K 1.000K 2 R 2 1236 0 1.100K 0.900K 1.010K 0.0032 10.295 8.9360 1.1000 0.9000  

RPR307
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR307 F3 T 2 2 100.0  

Pin Nail Net Name
1 788 P_+VCCIO_EN_10
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
870 RPR307 1.000K 1.000K 2 R 2 788 0 1.100K 0.900K 1.020K 0.0007 51.216 42.175 1.1000 0.9000  

RPR323
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR323 F4 T 2 2 100.0  

Pin Nail Net Name
1 1223 P_VCCIO_PG_G2_10
2 405 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1001 RPR323 8.200K 8.200K 2 R 405 1223 0 9.020K 7.380K 8.270K 0.0033 83.739 76.117 9.0200 7.3800  

RPR328
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR328 F4 T 2 2 100.0  

Pin Nail Net Name
1 1224 P_VCCIO_PG_G1_10
2 946 VCCIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1019 RPR328 8.200K 8.200K 2 R 946 1224 0 9.020K 7.380K 8.270K 0.0047 57.739 52.650 9.0200 7.3800  

RPR407
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR407 A2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 98 P_3V_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
877 RPR407 1.500K 1.500K 2 R 1 98 5 1.650K 1.350K 1.510K 0.0033 15.266 13.899 1.6500 1.3500  

RPR413
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR413 B2 T 2 2 100.0  

Pin Nail Net Name
1 525 P_+3V_OV_ER_10
2 528 P_+3V_OV_E_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
803 RPR413 499.00 499.00 2 R 528 525 0 698.60 299.40 475.54 0.1592 417.91 368.79 698.60 299.40  

RPR415
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR415 A2 T 2 2 100.0  

Pin Nail Net Name
1 101 P_+3V_OV_REF_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1038 RPR415 8.200K 8.200K 2 R 1 101 2 9.020K 7.380K 8.040K 0.0071 38.684 31.276 9.0200 7.3800  

RPR416
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR416 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 528 P_+3V_OV_E_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
966 RPR416 8.200K 8.200K 2 R 1 528 525 9.020K 7.380K 8.050K 0.0066 41.214 33.531 9.0200 7.3800  

RPR418
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR418 B2 T 2 2 100.0  

Pin Nail Net Name
1 399 +3VSB_ATX
2 525 P_+3V_OV_ER_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
804 RPR418 499.00 499.00 2 R 399 525 0 698.60 299.40 482.01 0.5160 128.93 117.96 698.60 299.40  

RPR421
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR421 A2 T 2 2 100.0  

Pin Nail Net Name
1 98 P_3V_GATE_10
2 5 -12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1053 RPR421 10.00K 10.00K 2 R 5 98 1 11.00K 9.00K 10.12K 0.0221 15.115 13.268 11.000 9.0000  

RPR426
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR426 A2 T 2 2 100.0  

Pin Nail Net Name
1 100 P_+3V_OV_G_10
2 793 +3V_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1014 RPR426 8.200K 8.200K 2 R 793 100 0 9.020K 7.380K 8.280K 0.0043 63.988 58.082 9.0200 7.3800  

RPR429
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR429 A2 T 2 2 100.0  

Pin Nail Net Name
1 100 P_+3V_OV_G_10
2 99 P_+3V_OV_G1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1016 RPR429 8.200K 8.200K 2 R 100 99 0 9.020K 7.380K 8.230K 0.0041 66.295 63.799 9.0200 7.3800  

RPR431
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR431 A2 T 2 2 100.0  

Pin Nail Net Name
1 101 P_+3V_OV_REF_10
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
867 RPR431 1.000K 1.000K 2 R 2 101 1 1.100K 0.900K 1.010K 0.0005 61.877 53.417 1.1000 0.9000  

RPR503
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR503 F4 T 2 2 100.0  

Pin Nail Net Name
1 1159 P_VDDQ_FB_10
2 360 P_+VDDQ_OV_1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
984 RPR503 8.200K 8.200K 2 R 1159 360 0 9.020K 7.380K 8.270K 0.0052 52.206 47.680 9.0200 7.3800  

RPR504
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR504 F4 T 2 2 100.0  

Pin Nail Net Name
1 1159 P_VDDQ_FB_10
2 369 P_+VDDQ_OV_2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
909 RPR504 4.420K 4.420K 2 R 1159 369 0 4.862K 3.978K 4.470K 0.0019 78.029 68.763 4.8600 3.9800  

RPR505
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR505 F4 T 2 2 100.0  

Pin Nail Net Name
1 1159 P_VDDQ_FB_10
2 393 P_+VDDQ_OV_3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
883 RPR505 2.430K 2.430K 2 R 1159 393 0 2.673K 2.187K 2.470K 0.0022 36.604 30.850 2.6700 2.1900  

RPR508
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR508 F4 T 2 2 100.0  

Pin Nail Net Name
1 129 S_SLP_S4_
2 1162 P_SLP_S4__R1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1075 RPR508 10.00K 10.00K 2 R 129 1162 0 11.00K 9.00K 10.12K 0.0062 53.524 46.943 11.000 9.0000  

RPR531
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR531 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1159 P_VDDQ_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
817 RPR531 732.00 732.00 2 R 1 1159 1168 1024.80 439.20 747.35 6.0562 16.116 15.271 1024.8 439.20  

RPR533
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR533 F4 T 2 2 100.0  

Pin Nail Net Name
1 1159 P_VDDQ_FB_10
2 1168 P_VDDQ_FB_SHORTPIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
800 RPR533 499.00 499.00 2 R 1168 1159 1 698.60 299.40 563.50 0.7820 85.079 57.586 698.60 299.40  

RPR535
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR535 F4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1146 P_VDDQ_LGATE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1091 RPR535 25.50K 25.50K 2 R 1 1146 0 28.05K 22.95K 25.93K 0.0462 18.404 15.303 28.050 22.950  

RPR537
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR537 F4 T 2 2 100.0  

Pin Nail Net Name
1 1166 P_VDDQ_COMP_10
2 1160 P_VDDQ_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1094 RPR537 32.40K 32.40K 2 R 1166 1160 0 35.64K 29.16K 33.15K 0.0751 14.381 11.040 35.640 29.160  

RPR540
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR540 F4 T 2 2 100.0  

Pin Nail Net Name
1 1169 P_VDDQ_REFOUT_10
2 1167 P_VDDQ_OFS_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
778 RPR540 255.00 255.00 2 R 1167 1169 0 357.00 153.00 260.95 0.3423 99.324 93.530 357.00 153.00  

RPR542
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR542 C4 T 2 2 100.0  

Pin Nail Net Name
1 710 P_VTT_DDR_REFIN_10
2 1148 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1073 RPR542 10.00K 10.00K 2 R 1148 710 1 11.00K 9.00K 10.51K 0.0146 22.784 11.142 11.000 9.0000  

RPR545
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR545 C4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 710 P_VTT_DDR_REFIN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1062 RPR545 10.00K 10.00K 2 R 1 710 1148 11.00K 9.00K 10.38K 0.0237 14.048 8.6950 11.000 9.0000  

RPR546
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR546 C3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 702 P_VTT_DDR_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1017 RPR546 8.200K 8.200K 2 R 2 702 0 9.020K 7.380K 8.260K 0.0071 38.570 35.588 9.0200 7.3800  

RPR550
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR550 F4 T 2 2 100.0 Parallel RPR620

Pin Nail Net Name
1 581 O_3VSBSW_
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
857 RPR550/R 1.000K 0.890K 2 R 797 581 0 0.979K 0.801K 0.900K 0.0007 40.685 34.573 0.9800 0.8000  

RPR551
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR551 F4 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 1161 P_+VDDQ_G_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1021 RPR551 8.200K 8.200K 2 R 797 1161 0 9.020K 7.380K 8.240K 0.0065 41.975 39.830 9.0200 7.3800  

RPR552
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR552 F4 T 2 2 100.0  

Pin Nail Net Name
1 1165 P_+VDDQ_S
2 1148 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
759 RPR552 51.00 51.00 2 R 1148 1165 0 71.40 30.60 53.34 0.0211 322.40 285.45 71.400 30.600  

RPR553
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR553 F4 T 2 2 100.0  

Pin Nail Net Name
1 1173 P_+VDDQ_PG1_10
2 1148 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
840 RPR553 1.000K 1.000K 2 R 1148 1173 0 1.100K 0.900K 1.010K 0.0006 52.068 44.962 1.1000 0.9000  

RPR554
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR554 F4 T 2 2 100.0  

Pin Nail Net Name
1 1173 P_+VDDQ_PG1_10
2 1170 P_+VDDQ_PG_B1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1076 RPR554 10.00K 10.00K 2 R 1170 1173 0 11.00K 9.00K 9.76K 0.0103 32.393 24.478 11.000 9.0000  

RPR556
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR556 F4 T 2 2 100.0  

Pin Nail Net Name
1 1171 P_+VDDQ_PG_B2_10
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1063 RPR556 10.00K 10.00K 2 R 797 1171 0 11.00K 9.00K 10.09K 0.0027 122.47 111.95 11.000 9.0000  

RPR559
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR559 F4 T 2 2 100.0  

Pin Nail Net Name
1 1164 P_VDDQ_COMP_GATE_10
2 581 O_3VSBSW_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1103 RPR559 40.20K 40.20K 2 R 1164 581 0 44.22K 36.18K 40.28K 0.1981 6.7650 6.6330 44.220 36.180  

RPR560
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR560 F4 T 2 2 100.0  

Pin Nail Net Name
1 1172 P_+5V_R1_10
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1099 RPR560 40.20K 40.20K 2 R 3 1172 1 44.22K 36.18K 40.38K 0.0047 283.82 270.95 44.220 36.180  

RPR565
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR565 B3 T 2 2 100.0  

Pin Nail Net Name
1 406 DDR_VTT_CNTL_B_R_10
2 707 DDR_VTT_CNTL_B_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
869 RPR565 1.000K 1.000K 2 R 707 406 0 1.100K 0.900K 1.010K 0.0008 43.220 37.455 1.1000 0.9000  

RPR567
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR567 B3 T 2 2 100.0  

Pin Nail Net Name
1 706 P_DDR_VTT_C_10
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1005 RPR567 8.200K 8.200K 2 R 797 706 0 9.020K 7.380K 8.280K 0.0058 46.991 42.677 9.0200 7.3800  

RPR568
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR568 F4 T 2 2 100.0  

Pin Nail Net Name
1 1172 P_+5V_R1_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1079 RPR568 13.00K 13.00K 2 R 1 1172 3 14.30K 11.70K 13.12K 0.0171 25.354 22.993 14.300 11.700  

RPR599
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR599 E4 T 2 2 100.0  

Pin Nail Net Name
1 1147 P_VDDQ_PHASE_20
2 1149 P_VDDQ_UGATE_M_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1000 RPR599 8.200K 8.200K 2 R 1147 1149 1 9.430K 6.970K 8.770K 0.4414 0.9290 0.4970 9.4300 6.9700  

RPR601
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR601 B4 T 2 2 100.0  

Pin Nail Net Name
1 356 P_+5VSB_ATX_OV_E_10
2 355 P_+5VSB_ATX_OV_E_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
807 RPR601 499.00 499.00 2 R 356 355 0 698.60 299.40 478.05 0.3055 217.81 194.95 698.60 299.40  

RPR603
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR603 B4 T 2 2 100.0  

Pin Nail Net Name
1 357 P_+5VSB_ATX_OV_REF_10
2 405 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
906 RPR603 2.940K 2.940K 2 R 405 357 1 3.234K 2.646K 3.070K 0.0088 11.179 6.0980 3.2300 2.6500  

RPR604
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR604 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 357 P_+5VSB_ATX_OV_REF_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
918 RPR604 4.700K 4.700K 2 R 1 357 405 5.170K 4.230K 4.720K 0.0025 62.794 60.602 5.1700 4.2300  

RPR605
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR605 B4 T 2 2 100.0  

Pin Nail Net Name
1 355 P_+5VSB_ATX_OV_E_R_10
2 399 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
808 RPR605 499.00 499.00 2 R 399 355 0 698.60 299.40 479.46 0.1953 340.59 307.24 698.60 299.40  

RPR606
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR606 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 356 P_+5VSB_ATX_OV_E_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1007 RPR606 8.200K 8.200K 2 R 1 356 355 9.020K 7.380K 8.030K 0.0056 48.693 38.561 9.0200 7.3800  

RPR607
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR607 B4 T 2 2 100.0  

Pin Nail Net Name
1 358 P_+5VSB_ATX_OV_G_10
2 368 P_+5VSB_ATX_OV_B_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1056 RPR607 10.00K 10.00K 2 R 358 368 0 11.00K 9.00K 10.09K 0.0088 37.858 34.536 11.000 9.0000  

RPR608
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR608 B4 T 2 2 100.0  

Pin Nail Net Name
1 358 P_+5VSB_ATX_OV_G_10
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1074 RPR608 10.00K 10.00K 2 R 797 358 0 11.00K 9.00K 10.11K 0.0067 49.434 43.859 11.000 9.0000  

RPR609
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR609 C4 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 792 P_5VSB_SHORT_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
788 RPR609 470.00 470.00 2 R 797 792 0 658.00 282.00 478.92 0.2404 260.70 248.32 658.00 282.00  

RPR610
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR610 B4 T 2 2 100.0  

Pin Nail Net Name
1 377 P_5VSB_GATE_10_1
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1002 RPR610 8.200K 8.200K 2 R 797 377 370 9.020K 7.380K 8.240K 0.0048 57.379 54.541 9.0200 7.3800  

RPR611
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR611 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 378 P_5VSB_Q3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
916 RPR611 4.700K 4.700K 2 R 1 378 359 5.170K 4.230K 4.740K 0.0011 146.93 135.96 5.1700 4.2300  

RPR612
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR612 B4 T 2 2 100.0  

Pin Nail Net Name
1 365 P_5VSB_GATE1_10
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1100 RPR612 40.20K 40.20K 2 R 4 365 0 44.22K 36.18K 40.56K 0.0083 161.08 146.79 44.220 36.180  

RPR613
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR613 B4 T 2 2 100.0  

Pin Nail Net Name
1 378 P_5VSB_Q3_10
2 359 P_5VSB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
967 RPR613 8.200K 8.200K 2 R 359 378 1 9.020K 7.380K 8.280K 0.0045 61.163 55.304 9.0200 7.3800  

RPR614
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR614 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 366 P_5VSB_Q2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
914 RPR614 4.700K 4.700K 2 R 1 366 359 5.170K 4.230K 4.710K 0.0075 20.933 20.659 5.1700 4.2300  

RPR615
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR615 B4 T 2 2 100.0  

Pin Nail Net Name
1 366 P_5VSB_Q2_10
2 359 P_5VSB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1009 RPR615 8.200K 8.200K 2 R 359 366 1 9.020K 7.380K 8.280K 0.0179 15.232 13.788 9.0200 7.3800  

RPR616
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR616 C4 T 2 2 100.0  

Pin Nail Net Name
1 359 P_5VSB_Q1_10
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
917 RPR616 4.700K 4.700K 2 R 797 359 1 5.170K 4.230K 4.760K 0.0027 57.945 50.941 5.1700 4.2300  

RPR617
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR617 F4 T 2 2 100.0  

Pin Nail Net Name
1 1155 P_5V_DUAL_Q4_10
2 1157 P_5V_DUAL_Q3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
844 RPR617 1.000K 1.000K 2 R 1155 1157 0 1.100K 0.900K 1.010K 0.0005 63.962 55.456 1.1000 0.9000  

RPR618
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR618 F4 T 2 2 100.0  

Pin Nail Net Name
1 1155 P_5V_DUAL_Q4_10
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
949 RPR618 8.200K 8.200K 2 R 797 1155 0 9.020K 7.380K 8.290K 0.0045 60.691 54.220 9.0200 7.3800  

RPR619
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR619 F4 T 2 2 100.0  

Pin Nail Net Name
1 1156 P_5V_DUAL_C3_10
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
988 RPR619 8.200K 8.200K 2 R 797 1156 0 9.020K 7.380K 8.280K 0.0055 49.916 44.934 9.0200 7.3800  

RPR621
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR621 F4 T 2 2 100.0  

Pin Nail Net Name
1 1152 P_5V_DUAL__
2 1151 N16880461

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
993 RPR621 8.200K 8.200K 2 R 1151 1152 0 9.020K 7.380K 8.250K 0.0042 65.456 61.676 9.0200 7.3800  

RPR622
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR622 F4 T 2 2 100.0  

Pin Nail Net Name
1 1154 P_5V_DUAL_GATE_10
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
979 RPR622 8.200K 8.200K 2 R 4 1154 0 9.020K 7.380K 8.300K 0.0026 106.50 92.926 9.0200 7.3800  

RPR624
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR624 F4 T 2 2 100.0  

Pin Nail Net Name
1 1155 P_5V_DUAL_Q4_10
2 1153 P_5V_DUAL_Q2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
856 RPR624 1.000K 1.000K 2 R 1155 1153 0 1.100K 0.900K 1.020K 0.0008 43.172 36.570 1.1000 0.9000  

RPR625
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR625 C4 T 2 2 100.0  

Pin Nail Net Name
1 789 P_5VSB_B1_10
2 524 O_PWROK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
985 RPR625 8.200K 8.200K 2 R 524 789 0 9.020K 7.380K 8.210K 0.0072 38.129 37.810 9.0200 7.3800  

RPR627
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR627 B4 T 2 2 100.0  

Pin Nail Net Name
1 370 P_5VSB_GATE_R_10
2 367 P_5VSB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
860 RPR627 1.000K 1.000K 2 R 367 370 0 1.100K 0.900K 0.960K 0.0004 84.644 50.509 1.1000 0.9000  

RPR628
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR628 B4 T 2 2 100.0  

Pin Nail Net Name
1 377 P_5VSB_GATE_10_1
2 370 P_5VSB_GATE_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
863 RPR628 1.000K 1.000K 2 R 377 370 0 1.100K 0.900K 0.960K 0.0007 49.106 30.409 1.1000 0.9000  

RPR629
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR629 B4 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 370 P_5VSB_GATE_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1129 RPR629 100.00K 100.00K 2 R 797 370 377 110.00K 90.00K 97.92K 0.6946 4.7990 3.7990 110.00 90.000  

RPR630
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR630 B4 T 2 2 100.0  

Pin Nail Net Name
1 380 P_5VSB_GATE_RC_10
2 379 P_5VSB_GATE_B1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
865 RPR630 1.000K 1.000K 2 R 380 379 0 1.100K 0.900K 1.010K 0.0009 39.059 34.400 1.1000 0.9000  

RPR631
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR631 B4 T 2 2 100.0  

Pin Nail Net Name
1 381 P_5VSB_GATE_D_10
2 380 P_5VSB_GATE_RC_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1117 RPR631 100.00K 100.00K 2 R 380 381 377 110.00K 90.00K 101.17K 0.0444 75.149 66.366 110.00 90.000  

RPR632
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR632 A4 T 2 2 100.0  

Pin Nail Net Name
1 340 P_SLPS3__C1_10
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1033 RPR632 8.200K 8.200K 2 R 3 340 1 9.020K 7.380K 8.270K 0.0078 35.255 32.284 9.0200 7.3800  

RPR633
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR633 A4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 340 P_SLPS3__C1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1036 RPR633 8.200K 8.200K 2 R 1 340 3 9.020K 7.380K 8.260K 0.0093 29.440 27.335 9.0200 7.3800  

RPR634
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR634 A4 T 2 2 100.0  

Pin Nail Net Name
1 341 P_SLPS3__R_10
2 427 S_SLP_S3_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
978 RPR634 8.200K 8.200K 2 R 427 341 0 9.020K 7.380K 8.250K 0.0035 79.083 74.058 9.0200 7.3800  

RPR701
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR701 B2 T 2 2 100.0  

Pin Nail Net Name
1 522 P_+3VSB_ATX_ADJ_20
2 399 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
873 RPR701 1.270K 1.270K 2 R 399 522 1 1.397K 1.143K 1.300K 0.0011 37.181 28.946 1.4000 1.1400  

RPR702
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR702 B4 T 2 2 100.0  

Pin Nail Net Name
1 386 P_+1_0V_A_FB_R_10
2 385 P_+1_0V_A_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
933 RPR702 6.040K 6.040K 2 R 385 386 400 6.644K 5.436K 6.110K 0.0132 15.197 13.543 6.6400 5.4400  

RPR707
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR707 B4 T 2 2 100.0  

Pin Nail Net Name
1 386 P_+1_0V_A_FB_R_10
2 400 P_+1_0V_A_VOUT_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
799 RPR707 499.00 499.00 2 R 400 386 0 698.60 299.40 490.90 0.1640 405.62 389.15 698.60 299.40  

RPR708
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR708 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 385 P_+1_0V_A_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1070 RPR708 10.00K 10.00K 2 R 1 385 386 11.00K 9.00K 10.00K 0.0091 36.602 36.481 11.000 9.0000  

RPR712
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR712 B4 T 2 2 100.0  

Pin Nail Net Name
1 392 P_+1_0V_A_OV1_10
2 386 P_+1_0V_A_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
920 RPR712 4.700K 4.700K 2 R 392 386 0 5.170K 4.230K 4.740K 0.0010 151.00 138.00 5.1700 4.2300  

RPR713
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR713 A4 T 2 2 100.0  

Pin Nail Net Name
1 388 P_+1_8V_A_PG_10
2 405 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1059 RPR713 10.00K 10.00K 2 R 388 405 1 11.00K 9.00K 10.06K 0.4384 0.7600 0.7150 11.000 9.0000  

RPR717
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR717 A4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 388 P_+1_8V_A_PG_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1077 RPR717 10.00K 10.00K 2 R 1 388 405 11.00K 9.00K 9.30K 0.1229 2.7130 0.8160 11.000 9.0000  

RPR718
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR718 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 522 P_+3VSB_ATX_ADJ_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
882 RPR718 2.150K 2.150K 2 R 1 522 399 2.365K 1.935K 2.180K 0.0015 47.124 41.061 2.3700 1.9400  

RPR739
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR739 B4 T 2 2 100.0 Parallel CPC736

Pin Nail Net Name
1 390 P_+1_0V_A_FBR_10
2 398 P_+1_0V_A_SW_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1136 RPR739/C 1.000M 1.000M 2 R 390 398 385 1.300M 0.600M 0.670M 0.0240 4.8550 0.9230 1.3000 0.6000  

RPR740
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR740 B4 T 2 2 100.0  

Pin Nail Net Name
1 385 P_+1_0V_A_FB_10
2 390 P_+1_0V_A_FBR_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
801 RPR740 499.00 499.00 2 R 385 390 0 698.60 299.40 505.95 0.0488 1363.8 1316.4 698.60 299.40  

RPR741
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR741 B3 T 2 2 100.0  

Pin Nail Net Name
1 129 S_SLP_S4_
2 422 P_VCCST_VCCSFR_B_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1068 RPR741 10.00K 10.00K 2 R 129 422 0 11.00K 9.00K 10.12K 0.0062 53.872 47.422 11.000 9.0000  

RPR743
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR743 B3 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 413 P_VCCST_VCCSFR_D1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
944 RPR743 8.200K 8.200K 2 R 797 413 0 9.020K 7.380K 8.110K 0.0447 6.1200 5.4270 9.0200 7.3800  

RPR744
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR744 B3 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 423 P_VCCST_VCCSFR_C_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1098 RPR744 40.20K 40.20K 2 R 797 423 0 44.22K 36.18K 40.37K 0.0137 97.522 93.289 44.220 36.180  

RPR755
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR755 D1 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 957 P_VCCSA_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
878 RPR755 1.960K 1.960K 2 R 1 957 966 2.156K 1.764K 1.850K 0.0035 18.556 7.8020 2.1600 1.7600  

RPR756
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR756 D2 T 2 2 100.0  

Pin Nail Net Name
1 956 P_VCCSA_REFOUT_10
2 955 P_VCCSA_OFS_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
777 RPR756 255.00 255.00 2 R 955 956 0 357.00 153.00 262.64 0.3217 105.69 97.779 357.00 153.00  

RPR759
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR759 D1 T 2 2 100.0  

Pin Nail Net Name
1 969 P_VCCSA_COMP_10
2 967 P_VCCSA_FB_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1095 RPR759 32.40K 32.40K 2 R 969 967 0 35.64K 29.16K 32.91K 0.0493 21.926 18.451 35.640 29.160  

RPR760
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR760 D2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 959 P_VCCSA_LGATE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1092 RPR760 25.50K 25.50K 2 R 1 959 0 28.05K 22.95K 25.95K 0.0285 29.847 24.534 28.050 22.950  

RPR762
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR762 D1 T 2 2 100.0  

Pin Nail Net Name
1 957 P_VCCSA_FB_10
2 966 P_VCCSA_FB_SHORTPIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
802 RPR762 499.00 499.00 2 R 966 957 968 698.60 299.40 442.06 0.8695 76.522 54.692 698.60 299.40  

RPR764
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR764 D2 T 2 2 100.0 Parallel QPQ710_3_4

Pin Nail Net Name
1 950 P_VCCSA_PHASE_20
2 963 P_VCCSA_UGATE_M_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1004 RPR764/Q 8.200K 8.200K 2 R 950 963 1 9.020K 6.560K 7.660K 0.0243 16.874 15.154 9.0200 6.5600  

RPR767
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR767 D1 T 2 2 100.0  

Pin Nail Net Name
1 970 P_VCCSA_C1_10
2 405 +5VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1051 RPR767 8.200K 8.200K 2 R 405 970 0 9.020K 7.380K 8.280K 0.0036 75.043 67.625 9.0200 7.3800  

RPR768
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR768 D1 T 2 2 100.0  

Pin Nail Net Name
1 971 P_VCCSA_B1_10
2 788 P_+VCCIO_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
822 RPR768 1.000K 1.000K 2 R 788 971 0 1.100K 0.900K 1.010K 0.0001 481.13 428.55 1.1000 0.9000  

RPR769
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR769 D1 T 2 2 100.0  

Pin Nail Net Name
1 425 P_+VCCSAIO_OV__1_10
2 957 P_VCCSA_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
990 RPR769 8.200K 8.200K 2 R 957 425 0 9.020K 7.380K 8.250K 0.0028 99.281 92.633 9.0200 7.3800  

RPR770
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR770 B2 T 2 2 100.0 Parallel RPR773

Pin Nail Net Name
1 1 GND
2 793 +3V_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
762 RPR770/RPR773 100.00 33.33 2 R 1 793 0 46.66 20.00 34.09 0.0341 130.19 122.77 46.660 20.000  

RPR779
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR779 B3 T 2 2 100.0  

Pin Nail Net Name
1 424 P_+12V_DUMMY_R2
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
775 RPR779 180.00 180.00 2 R 4 424 0 252.00 108.00 183.84 0.2262 106.11 100.46 252.00 108.00  

RPR782
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR782 D1 T 2 2 100.0  

Pin Nail Net Name
1 705 P_+VCCSAIO_OV__2_10
2 957 P_VCCSA_FB_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
908 RPR782 4.020K 4.020K 2 R 957 705 0 4.422K 3.618K 4.040K 0.0014 96.871 91.140 4.4200 3.6200  

RPR801
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR801 F3 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 1231 P_VREN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
915 RPR801 4.700K 4.700K 2 R 797 1231 0 5.170K 4.230K 4.730K 0.0022 70.866 66.050 5.1700 4.2300  

RPR802
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR802 F3 T 2 2 100.0  

Pin Nail Net Name
1 384 P_VR_READY_10
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
826 RPR802 1.000K 1.000K 2 R 2 384 0 1.100K 0.900K 1.010K 0.0003 101.12 88.941 1.1000 0.9000  

RPR803
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR803 F3 T 2 2 100.0  

Pin Nail Net Name
1 427 S_SLP_S3_
2 1230 P_VREN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1055 RPR803 10.00K 10.00K 2 R 427 1230 0 11.00K 9.00K 10.12K 0.0102 32.698 28.797 11.000 9.0000  

RPR805
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR805 F4 T 2 2 100.0  

Pin Nail Net Name
1 1234 P_VCORE_PG__10
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1011 RPR805 8.200K 8.200K 2 R 797 1234 0 9.020K 7.380K 8.260K 0.0015 182.68 169.70 9.0200 7.3800  

RPR808
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR808 F3 T 2 2 100.0  

Pin Nail Net Name
1 405 +5VSB
2 1227 P_+12V_3V_EN_C1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1105 RPR808 40.20K 40.20K 2 R 405 1227 0 44.22K 36.18K 40.58K 0.0084 160.18 145.00 44.220 36.180  

RPR809
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR809 F3 T 2 2 100.0  

Pin Nail Net Name
1 1339 +12V_CPU
2 1228 P_+12V_3V_EN_R1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1093 RPR809 27.00K 27.00K 2 R 1339 1228 1 29.70K 24.30K 25.69K 0.1414 6.3660 3.2820 29.700 24.300  

RPR812
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR812 F3 T 2 2 100.0  

Pin Nail Net Name
1 1228 P_+12V_3V_EN_R1_10
2 1226 P_+12V_3V_EN_B1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1065 RPR812 10.00K 10.00K 2 R 1226 1228 1 11.00K 9.00K 10.05K 0.0083 40.034 37.954 11.000 9.0000  

RPR814
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR814 F3 T 2 2 100.0  

Pin Nail Net Name
1 1228 P_+12V_3V_EN_R1_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
907 RPR814 3.900K 3.900K 2 R 1 1228 1226 4.290K 3.120K 3.490K 0.0057 34.324 21.873 4.2900 3.1200  

RPR815
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR815 F3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 1241 P_+12V_3V_EN_R2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1069 RPR815 10.00K 10.00K 2 R 2 1241 1 11.00K 9.00K 10.19K 0.0070 47.932 38.987 11.000 9.0000  

RPR816
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR816 F3 T 2 2 100.0  

Pin Nail Net Name
1 1241 P_+12V_3V_EN_R2_10
2 1240 P_+12V_3V_EN_B2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1072 RPR816 10.00K 10.00K 2 R 1240 1241 1 11.00K 9.00K 9.72K 0.0157 21.236 15.378 11.000 9.0000  

RPR817
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR817 F3 T 2 2 100.0  

Pin Nail Net Name
1 1241 P_+12V_3V_EN_R2_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
932 RPR817 5.600K 5.600K 2 R 1 1241 2 6.160K 5.040K 5.670K 0.0039 47.848 41.813 6.1600 5.0400  

RPR826
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR826 C4 T 2 2 100.0  

Pin Nail Net Name
1 383 P_5V_USB_Q1_10
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
923 RPR826 4.700K 4.700K 2 R 797 383 107 5.170K 4.230K 4.760K 0.0033 47.766 41.448 5.1700 4.2300  

RPR827
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR827 B4 T 2 2 100.0  

Pin Nail Net Name
1 363 P_5V_USB_Q2_10
2 383 P_5V_USB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1006 RPR827 8.200K 8.200K 2 R 383 363 1 9.020K 7.380K 8.240K 0.0048 56.735 53.641 9.0200 7.3800  

RPR829
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR829 B4 T 2 2 100.0  

Pin Nail Net Name
1 362 P_5V_USB_Q3_10
2 383 P_5V_USB_Q1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
982 RPR829 8.200K 8.200K 2 R 383 362 1 9.020K 7.380K 8.270K 0.0049 56.289 51.721 9.0200 7.3800  

RPR830
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR830 C4 T 2 2 100.0  

Pin Nail Net Name
1 790 P_5V_USB_GATE_10
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1101 RPR830 40.20K 40.20K 2 R 4 790 0 44.22K 36.18K 40.64K 0.0068 196.52 175.25 44.220 36.180  

RPR832
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR832 B4 T 2 2 100.0  

Pin Nail Net Name
1 376 P_5VSB_USB_GATE_10_1
2 797 +5VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1008 RPR832 8.200K 8.200K 2 R 797 376 791 9.020K 7.380K 8.250K 0.0031 88.349 82.823 9.0200 7.3800  

RPR837
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR837 B4 T 2 2 100.0  

Pin Nail Net Name
1 791 N16717470
2 361 P_5VSB_USB_GATE_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
919 RPR837 4.700K 4.700K 2 R 361 791 0 5.170K 4.230K 4.660K 0.0028 56.116 51.242 5.1700 4.2300  

RPTR101
Device Loc Side Total Pin Tested Coverage (%) Comment
RPTR101 F2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1294 P_GT_TMA_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1130 RPTR101 10.00K 10.00K 2 R 1294 1 1263 13.00K 6.50K 7.43K 0.0199 54.571 15.555 13.000 6.5000  

RPTR102
Device Loc Side Total Pin Tested Coverage (%) Comment
RPTR102 F3 T 2 2 100.0 Parallel RPR131

Pin Nail Net Name
1 1300 P_GT_CSPA_R_10
2 1289 P_GT_CSCOMPA_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1120 RPTR102/RPR13 100.00K 45.21K 2 R 1289 1300 1 58.77K 31.65K 36.87K 0.0866 52.212 20.112 58.770 31.650  

RPTR103
Device Loc Side Total Pin Tested Coverage (%) Comment
RPTR103 F2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 1315 P_VCORE_TM_R_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1116 RPTR103 10.00K 10.00K 2 R 1315 1 1265 13.00K 6.50K 7.39K 0.0417 25.964 7.0830 13.000 6.5000  

RPTR104
Device Loc Side Total Pin Tested Coverage (%) Comment
RPTR104 F2 T 2 2 100.0 Parallel RPR136

Pin Nail Net Name
1 1314 P_VCORE_CSP_R_10
2 1317 P_VCORE_CSCOMP_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1127 RPTR104/RPR13 100.00K 50.00K 2 R 1317 1314 1 65.00K 35.00K 38.21K 0.0901 55.465 11.876 65.000 35.000  

RSR10
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR10 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 142 N96817951

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
835 RSR10 1.000K 1.000K 2 R 1 142 0 1.100K 0.900K 1.010K 0.0004 94.604 85.414 1.1000 0.9000  

RSR100
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR100 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 82 S_SERIRQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
947 RSR100 8.200K 8.200K 2 R 2 82 0 9.020K 7.380K 8.020K 0.0037 74.096 58.205 9.0200 7.3800  

RSR1000
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1000 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 93 PCIEX1_SL2_PRSNT_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
972 RSR1000 8.200K 8.200K 2 R 2 93 0 9.020K 7.380K 8.240K 0.0055 49.259 46.776 9.0200 7.3800  

RSR1001
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1001 A4 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 262 S_GPP_H1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
973 RSR1001 8.200K 8.200K 2 R 2 262 0 9.020K 7.380K 8.250K 0.0039 70.976 66.854 9.0200 7.3800  

RSR1002
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1002 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 248 S_GPP_H2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
983 RSR1002 8.200K 8.200K 2 R 2 248 0 9.020K 7.380K 8.260K 0.0048 56.877 52.652 9.0200 7.3800  

RSR1003
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1003 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 234 S_GPP_H3

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
989 RSR1003 8.200K 8.200K 2 R 2 234 0 9.020K 7.380K 8.290K 0.0059 46.704 41.529 9.0200 7.3800  

RSR1004
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1004 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 500 PCIEX16_SL1_PRSNT_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1023 RSR1004 8.200K 8.200K 2 R 2 500 0 9.020K 7.380K 8.250K 0.0061 45.138 42.393 9.0200 7.3800  

RSR1005
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1005 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 529 PCIEX1_SL1_PRSNT_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1025 RSR1005 8.200K 8.200K 2 R 2 529 0 9.020K 7.380K 8.290K 0.0049 55.772 49.875 9.0200 7.3800  

RSR1006
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1006 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 270 S_GPP_H9

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1029 RSR1006 8.200K 8.200K 2 R 2 270 0 9.020K 7.380K 8.250K 0.0055 50.012 47.200 9.0200 7.3800  

RSR11
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR11 B3 T 2 2 100.0  

Pin Nail Net Name
1 450 +1_0V_A_XCLK_BIAS
2 448 S_XCLK_BIASREF

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
890 RSR11 2.700K 2.700K 2 R 450 448 0 2.970K 2.430K 2.700K 0.0064 13.959 13.803 2.9700 2.4300  

RSR118
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR118 C2 T 2 2 100.0  

Pin Nail Net Name
1 682 +BAT
2 681 +BAT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
837 RSR118 1.000K 1.000K 2 R 681 682 0 1.100K 0.900K 1.010K 0.0006 59.457 51.705 1.1000 0.9000  

RSR119
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR119 A2 T 2 2 100.0  

Pin Nail Net Name
1 71 +3V_BAT
2 103 +3V_BAT_RTC

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1081 RSR119 18.70K 18.70K 2 R 71 103 1 20.57K 16.83K 18.80K 0.0244 25.548 24.230 20.570 16.830  

RSR120
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR120 A2 T 2 2 100.0  

Pin Nail Net Name
1 114 S_RTCRST_
2 103 +3V_BAT_RTC

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
838 RSR120 1.000K 1.000K 2 R 103 114 0 1.100K 0.900K 0.970K 0.0009 37.714 26.125 1.1000 0.9000  

RSR121
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR121 A2 T 2 2 100.0  

Pin Nail Net Name
1 71 +3V_BAT
2 115 S_SRTCRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1087 RSR121 20.00K 20.00K 2 R 115 71 1 22.00K 18.00K 20.13K 0.0609 10.944 10.244 22.000 18.000  

RSR122
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR122 A3 T 2 2 100.0  

Pin Nail Net Name
1 187 L1_LAN_WAKE_
2 144 +3VSB_ADV

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1084 RSR122 20.00K 20.00K 2 R 144 187 0 22.00K 18.00K 20.31K 0.0214 31.104 26.325 22.000 18.000  

RSR125
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR125 A3 T 2 2 100.0  

Pin Nail Net Name
1 165 CK_24M_TPM_R
2 87 CK_24M_TPM

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
717 RSR125 22.00 22.00 0 R 87 165 0 30.80 13.20 23.52 0.0169 173.53 143.57 30.800 13.200  

RSR127
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR127 A4 T 2 2 100.0  

Pin Nail Net Name
1 328 N35695809
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1046 RSR127 8.200K 8.200K 2 R 549 328 0 9.020K 7.380K 8.260K 0.0058 47.465 44.276 9.0200 7.3800  

RSR129
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR129 C3 T 2 2 100.0  

Pin Nail Net Name
1 410 S_VCCST_PWRGD
2 426 VCCST_VCCSFR

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
839 RSR129 1.000K 1.000K 2 R 426 410 0 1.100K 0.900K 1.010K 0.0006 56.543 49.551 1.1000 0.9000  

RSR134
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR134 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 267 S_GPP_C7

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
981 RSR134 8.200K 8.200K 2 R 549 267 0 9.020K 7.380K 8.260K 0.0038 72.558 67.409 9.0200 7.3800  

RSR135
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR135 A4 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 290 S_GPP_C6

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
946 RSR135 8.200K 8.200K 2 R 549 290 0 9.020K 7.380K 8.250K 0.0028 99.160 92.752 9.0200 7.3800  

RSR14
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR14 B3 T 2 2 100.0  

Pin Nail Net Name
1 451 S_24M_IN
2 478 S_24M_OUT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1134 RSR14 1.000M 1.000M 2 R 478 451 1 1.300M 0.700M 0.960M 0.0006 164.96 145.66 1.3000 0.7000  

RSR145
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR145 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 168 S_GPP_A7

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
987 RSR145 8.200K 8.200K 2 R 549 168 0 9.020K 7.380K 8.290K 0.0081 33.610 29.787 9.0200 7.3800  

RSR152
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR152 B4 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 418 S_USB2_OCB_7

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
986 RSR152 8.200K 8.200K 2 R 549 418 0 9.020K 7.380K 8.250K 0.0044 62.401 58.747 9.0200 7.3800  

RSR1607
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1607 A3 T 2 2 100.0  

Pin Nail Net Name
1 164 S_RTCX1
2 160 S_RTCX2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1140 RSR1607 20.00M 20.00M 2 R 160 164 0 26.00M 14.00M 16.02M 0.2174 9.2010 3.0930 26.000 14.000  

RSR1628
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1628 A3 T 2 2 100.0  

Pin Nail Net Name
1 449 +1_0V_A
2 494 S_VCORE_SHDN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
945 RSR1628 8.200K 8.200K 2 R 449 494 140 9.020K 7.380K 8.210K 0.0057 47.609 47.198 9.0200 7.3800  

RSR163
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR163 B2 T 2 2 100.0  

Pin Nail Net Name
1 680 N74741034
2 399 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
879 RSR163 2.000K 2.000K 2 R 399 680 0 2.200K 1.800K 1.950K 0.0024 27.682 20.600 2.2000 1.8000  

RSR1633
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1633 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 247 S_GPP_H23

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
948 RSR1633 8.200K 8.200K 2 R 549 247 0 9.020K 7.380K 8.270K 0.0051 53.871 49.421 9.0200 7.3800  

RSR1642
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1642 A2 T 2 2 100.0  

Pin Nail Net Name
1 118 +3V_SPI
2 106 F_BIOS_WP_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
848 RSR1642 1.000K 1.000K 2 R 118 106 0 1.100K 0.900K 1.020K 0.0007 50.170 40.933 1.1000 0.9000  

RSR1643
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1643 A2 T 2 2 100.0  

Pin Nail Net Name
1 118 +3V_SPI
2 119 F_SPI_HOLD_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
849 RSR1643 1.000K 1.000K 2 R 118 119 0 1.100K 0.900K 1.010K 0.0009 37.368 31.805 1.1000 0.9000  

RSR1645
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1645 B3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 419 S_USB2_OCB_6

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
951 RSR1645 8.200K 8.200K 2 R 549 419 0 9.020K 7.380K 8.250K 0.0076 35.945 33.547 9.0200 7.3800  

RSR1652
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1652 A4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 281 S_GPP_D16

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
953 RSR1652 8.200K 8.200K 2 R 1 281 0 9.020K 7.380K 8.280K 0.0058 46.798 42.402 9.0200 7.3800  

RSR1654
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1654 B3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 396 S_GPP_G2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
954 RSR1654 8.200K 8.200K 2 R 1 396 0 9.020K 7.380K 8.150K 0.0033 82.133 76.913 9.0200 7.3800  

RSR1655
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1655 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 394 S_GPP_G3

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
955 RSR1655 8.200K 8.200K 2 R 1 394 0 9.020K 7.380K 8.210K 0.0028 99.171 97.799 9.0200 7.3800  

RSR1656
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1656 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 397 S_GPP_G4

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
956 RSR1656 8.200K 8.200K 2 R 1 397 0 9.020K 7.380K 8.240K 0.0050 55.078 52.461 9.0200 7.3800  

RSR166
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR166 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 289 L1_SMBDATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
957 RSR166 8.200K 8.200K 2 R 549 289 0 9.020K 7.380K 8.250K 0.0065 42.211 39.770 9.0200 7.3800  

RSR1666
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1666 A4 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 306 S_GPP_D22

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
959 RSR1666 8.200K 8.200K 2 R 549 306 0 9.020K 7.380K 8.280K 0.0055 49.924 45.234 9.0200 7.3800  

RSR1667
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1667 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 407 S_GPP_H18

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
960 RSR1667 8.200K 8.200K 2 R 549 407 0 9.020K 7.380K 8.270K 0.0048 56.914 52.077 9.0200 7.3800  

RSR1668
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1668 A4 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 409 S_GPP_H14

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
961 RSR1668 8.200K 8.200K 2 R 549 409 0 9.020K 7.380K 8.250K 0.0056 48.801 45.773 9.0200 7.3800  

RSR1669
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1669 A4 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 296 S_GPP_D21

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
962 RSR1669 8.200K 8.200K 2 R 549 296 0 9.020K 7.380K 8.260K 0.0083 33.005 30.747 9.0200 7.3800  

RSR167
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR167 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 254 L1_SMBCLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
963 RSR167 8.200K 8.200K 2 R 549 254 0 9.020K 7.380K 8.300K 0.0063 43.277 38.020 9.0200 7.3800  

RSR1670
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1670 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 244 S_GPP_H16

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
964 RSR1670 8.200K 8.200K 2 R 549 244 0 9.020K 7.380K 8.250K 0.0063 43.272 40.672 9.0200 7.3800  

RSR1671
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1671 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 246 S_GPP_H13

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
965 RSR1671 8.200K 8.200K 2 R 549 246 0 9.020K 7.380K 8.290K 0.0046 59.436 53.218 9.0200 7.3800  

RSR1682
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1682 A3 T 2 2 100.0  

Pin Nail Net Name
1 134 S_HD_RST_
2 162 S_HD_RST__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
718 RSR1682 22.00 22.00 2 R 162 134 0 30.80 13.20 23.89 0.0127 230.46 180.93 30.800 13.200  

RSR1683
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1683 A3 T 2 2 100.0  

Pin Nail Net Name
1 69 S_HD_SDOUT
2 137 S_HD_SDOUT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
719 RSR1683 22.00 22.00 0 R 137 69 0 30.80 13.20 23.70 0.0163 180.25 145.42 30.800 13.200  

RSR1684
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1684 A3 T 2 2 100.0  

Pin Nail Net Name
1 135 S_HD_SYNC
2 163 S_HD_SYNC_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
720 RSR1684 22.00 22.00 2 R 163 135 0 30.80 13.20 23.97 0.0083 353.83 274.57 30.800 13.200  

RSR1685
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1685 A3 T 2 2 100.0  

Pin Nail Net Name
1 185 S_SX_EXIT_HOLDOFF_
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
968 RSR1685 8.200K 8.200K 2 R 549 185 0 9.020K 7.380K 8.240K 0.0074 37.136 35.542 9.0200 7.3800  

RSR1686
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1686 A3 T 2 2 100.0  

Pin Nail Net Name
1 189 S_GP_D0
2 144 +3VSB_ADV

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
969 RSR1686 8.200K 8.200K 2 R 144 189 0 9.020K 7.380K 8.250K 0.0060 45.654 43.047 9.0200 7.3800  

RSR1687
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1687 A3 T 2 2 100.0  

Pin Nail Net Name
1 184 S_GP_D1
2 144 +3VSB_ADV

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
970 RSR1687 8.200K 8.200K 2 R 144 184 0 9.020K 7.380K 8.250K 0.0071 38.744 36.511 9.0200 7.3800  

RSR1688
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1688 A3 T 2 2 100.0  

Pin Nail Net Name
1 208 S_VR_ALERT_
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
971 RSR1688 8.200K 8.200K 2 R 549 208 0 9.020K 7.380K 8.250K 0.0035 77.067 72.348 9.0200 7.3800  

RSR1689
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1689 A2 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 670 S_DVI_DDC_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
899 RSR1689 2.700K 2.700K 2 R 2 670 0 2.970K 2.430K 2.750K 0.0048 18.901 15.736 2.9700 2.4300  

RSR1690
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1690 A2 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 167 S_DVI_DDC_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
900 RSR1690 2.700K 2.700K 2 R 2 167 0 2.970K 2.430K 2.740K 0.0032 28.318 23.846 2.9700 2.4300  

RSR1715
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1715 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 182 S_GPP_A17

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
974 RSR1715 8.200K 8.200K 2 R 2 182 0 9.020K 7.380K 8.270K 0.0037 74.399 67.699 9.0200 7.3800  

RSR1716
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1716 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 491 S_GPP_A18

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
975 RSR1716 8.200K 8.200K 2 R 2 491 0 9.020K 7.380K 8.250K 0.0042 65.128 60.901 9.0200 7.3800  

RSR1717
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1717 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 204 S_GPP_A19

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
976 RSR1717 8.200K 8.200K 2 R 2 204 0 9.020K 7.380K 8.250K 0.0049 55.373 51.845 9.0200 7.3800  

RSR1718
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1718 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 207 S_GPP_A20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
977 RSR1718 8.200K 8.200K 2 R 2 207 0 9.020K 7.380K 8.250K 0.0038 71.950 67.876 9.0200 7.3800  

RSR1724
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1724 A4 T 2 2 100.0  

Pin Nail Net Name
1 330 S_SMBCLK_VSB
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
850 RSR1724 1.000K 1.000K 2 R 549 330 0 1.100K 0.900K 1.010K 0.0006 60.193 53.574 1.1000 0.9000  

RSR1725
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1725 A4 T 2 2 100.0  

Pin Nail Net Name
1 329 S_SMBDATA_VSB
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
851 RSR1725 1.000K 1.000K 2 R 549 329 0 1.100K 0.900K 1.010K 0.0008 40.278 35.558 1.1000 0.9000  

RSR1726
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1726 A4 T 2 2 100.0  

Pin Nail Net Name
1 712 S_SMBCLK_MAIN
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
852 RSR1726 1.000K 1.000K 2 R 2 712 0 1.100K 0.900K 1.010K 0.0006 56.691 48.599 1.1000 0.9000  

RSR1727
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1727 A4 T 2 2 100.0  

Pin Nail Net Name
1 770 S_SMBDATA_MAIN
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
853 RSR1727 1.000K 1.000K 2 R 2 770 0 1.100K 0.900K 1.010K 0.0008 39.896 34.715 1.1000 0.9000  

RSR1756
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1756 A4 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 307 S_GPP_D12

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
992 RSR1756 8.200K 8.200K 2 R 549 307 0 9.020K 7.380K 8.260K 0.0035 77.841 72.288 9.0200 7.3800  

RSR1762
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1762 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 280 S_GPP_C22

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
994 RSR1762 8.200K 8.200K 2 R 549 280 0 9.020K 7.380K 8.250K 0.0069 39.890 37.555 9.0200 7.3800  

RSR1763
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1763 A4 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 287 S_GPP_C20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
995 RSR1763 8.200K 8.200K 2 R 549 287 0 9.020K 7.380K 8.210K 0.0038 71.629 70.707 9.0200 7.3800  

RSR1764
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1764 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 250 S_GPP_H20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
996 RSR1764 8.200K 8.200K 2 R 549 250 0 9.020K 7.380K 8.250K 0.0033 81.887 76.602 9.0200 7.3800  

RSR1794
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1794 A4 T 2 2 100.0  

Pin Nail Net Name
1 304 S_SATALED__R
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
997 RSR1794 8.200K 8.200K 2 R 2 304 0 9.020K 7.380K 8.270K 0.0057 47.876 43.675 9.0200 7.3800  

RSR1795
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1795 A4 T 2 2 100.0  

Pin Nail Net Name
1 331 N45063647
2 2 +3V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
998 RSR1795 8.200K 8.200K 2 R 2 331 0 9.020K 7.380K 8.250K 0.0032 84.310 79.096 9.0200 7.3800  

RSR1796
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1796 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 138 S_DP2VGA_HPD

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1121 RSR1796 100.00K 100.00K 2 R 1 138 0 110.00K 90.00K 100.59K 0.0508 65.556 61.666 110.00 90.000  

RSR18
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR18 B3 T 2 2 100.0  

Pin Nail Net Name
1 438 S_PCIE_RCOMPN
2 439 S_PCIE_RCOMPP

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
766 RSR18 100.00 100.00 2 R 439 438 0 140.00 60.00 102.89 0.0564 236.57 219.50 140.00 60.000  

RSR202
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR202 A3 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 198 S_CLKRUN_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1003 RSR202 8.200K 8.200K 2 R 2 198 0 9.020K 7.380K 8.250K 0.0052 52.375 49.082 9.0200 7.3800  

RSR22
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR22 A3 T 2 2 100.0  

Pin Nail Net Name
1 141 S_USB2_COMP
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
774 RSR22 113.00 113.00 2 R 1 141 0 158.20 67.80 115.27 0.0614 245.37 233.03 158.20 67.800  

RSR242
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR242 A3 T 2 2 100.0  

Pin Nail Net Name
1 689 S_CPU_TRIGGER
2 150 S_CPU_TRIGGER_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
730 RSR242 30.00 30.00 0 R 150 689 0 42.00 18.00 32.12 0.0061 654.39 538.74 42.000 18.000  

RSR304
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR304 A4 T 2 2 100.0  

Pin Nail Net Name
1 338 N18147149
2 4 +12V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
859 RSR304 1.000K 1.000K 2 R 4 338 0 1.100K 0.900K 1.010K 0.0006 53.274 46.219 1.1000 0.9000  

RSR38
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR38 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 292 S_GPP_D13

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1013 RSR38 8.200K 8.200K 2 R 1 292 0 9.020K 7.380K 8.260K 0.0064 42.400 39.269 9.0200 7.3800  

RSR4
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR4 A3 T 2 2 100.0  

Pin Nail Net Name
1 166 CK_24M_SIO_R
2 78 CK_24M_SIO_LPC

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
721 RSR4 22.00 22.00 0 R 78 166 0 30.80 13.20 23.61 0.0184 159.54 130.42 30.800 13.200  

RSR40
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR40 A3 T 2 2 100.0  

Pin Nail Net Name
1 140 S_VCORE_SHDN__10_R
2 494 S_VCORE_SHDN__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
810 RSR40 560.00 560.00 2 R 494 140 0 784.00 336.00 568.75 0.1793 416.38 400.11 784.00 336.00  

RSR43
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR43 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 284 S_GPP_D14

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1015 RSR43 8.200K 8.200K 2 R 1 284 0 9.020K 7.380K 8.250K 0.0039 69.453 65.200 9.0200 7.3800  

RSR44
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR44 A3 T 2 2 100.0  

Pin Nail Net Name
1 151 S_PM_SYNC_R
2 685 S_PM_SYNC

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
731 RSR44 30.00 30.00 2 R 685 151 0 42.00 18.00 32.98 0.0330 121.27 91.189 42.000 18.000  

RSR49
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR49 A3 T 2 2 100.0  

Pin Nail Net Name
1 684 S_HDA_SDO_R
2 148 S_HDA_SDO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
745 RSR49 33.00 33.00 2 R 148 684 0 46.20 19.80 36.03 0.0125 351.20 270.70 46.200 19.800  

RSR5
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR5 A2 T 2 2 100.0  

Pin Nail Net Name
1 169 S_PLTRST__R
2 83 S_PLTRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
722 RSR5 22.00 22.00 0 R 83 169 0 30.80 13.20 23.61 0.0169 173.42 141.65 30.800 13.200  

RSR50
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR50 A3 T 2 2 100.0  

Pin Nail Net Name
1 679 S_HDA_SCLK
2 147 S_HDA_SCLK_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
746 RSR50 33.00 33.00 2 R 147 679 0 46.20 19.80 35.82 0.0307 143.41 112.79 46.200 19.800  

RSR52
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR52 A3 T 2 2 100.0  

Pin Nail Net Name
1 116 S_HD_BITCLK
2 155 S_HD_BITCLK_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
723 RSR52 22.00 22.00 2 R 155 116 0 30.80 13.20 24.12 0.0067 435.58 330.79 30.800 13.200  

RSR569
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR569 A3 T 2 2 100.0  

Pin Nail Net Name
1 229 S_SPI_MISO
2 105 F_SPI_MISO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
709 RSR569 15.00 15.00 0 R 105 229 0 21.00 9.00 16.49 0.0070 285.93 214.74 21.000 9.0000  

RSR57
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR57 E4 T 2 2 100.0  

Pin Nail Net Name
1 1095 S_D4_RESET__R
2 1148 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
793 RSR57 470.00 470.00 2 R 1148 1095 0 658.00 282.00 475.20 0.1030 608.51 591.68 658.00 282.00  

RSR570
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR570 A3 T 2 2 100.0  

Pin Nail Net Name
1 222 S_SPI_MOSI
2 121 F_SPI_MOSI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
710 RSR570 15.00 15.00 2 R 121 222 0 21.00 9.00 17.13 0.0090 223.27 144.18 21.000 9.0000  

RSR571
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR571 A3 T 2 2 100.0  

Pin Nail Net Name
1 232 S_SPI_CLK
2 120 F_SPI_CLK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
711 RSR571 15.00 15.00 2 R 120 232 0 21.00 9.00 17.21 0.0074 269.03 169.74 21.000 9.0000  

RSR573
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR573 A3 T 2 2 100.0  

Pin Nail Net Name
1 220 S_SPI_IO2
2 106 F_BIOS_WP_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
712 RSR573 15.00 15.00 2 R 106 220 0 21.00 9.00 17.12 0.0022 908.70 587.46 21.000 9.0000  

RSR574
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR574 A3 T 2 2 100.0  

Pin Nail Net Name
1 230 S_SPI_IO3
2 119 F_SPI_HOLD_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
713 RSR574 15.00 15.00 2 R 119 230 0 21.00 9.00 17.19 0.0057 353.67 224.69 21.000 9.0000  

RSR60
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR60 A3 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 543 S_WAKE_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
864 RSR60 1.000K 1.000K 2 R 549 543 0 1.100K 0.900K 1.010K 0.0006 53.172 47.509 1.1000 0.9000  

RSR701
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR701 B2 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 680 N74741034

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1106 RSR701 47.00K 47.00K 2 R 1 680 399 51.70K 42.30K 45.58K 0.0841 18.636 13.005 51.700 42.300  

RSR73
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR73 A4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 257 S_GPP_D15

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1028 RSR73 8.200K 8.200K 2 R 1 257 0 9.020K 7.380K 8.290K 0.0060 45.808 40.568 9.0200 7.3800  

RSR75
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR75 A3 T 2 2 100.0  

Pin Nail Net Name
1 149 S_CPUPWRGD_R
2 687 H_CPUPWRGD

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
732 RSR75 30.00 30.00 0 R 687 149 0 42.00 18.00 32.20 0.0247 162.10 132.40 42.000 18.000  

RSR801
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR801 B3 T 2 2 100.0  

Pin Nail Net Name
1 477 S_24M_IN_R
2 451 S_24M_IN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
724 RSR801 22.00 22.00 0 R 451 477 0 30.80 13.20 23.74 0.0034 851.79 683.14 30.800 13.200  

RSR87
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR87 A3 T 2 2 100.0  

Pin Nail Net Name
1 186 S_INTRUDER_
2 71 +3V_BAT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1137 RSR87 1.000M 1.000M 2 R 71 186 0 1.300M 0.700M 0.990M 0.0009 108.61 104.99 1.3000 0.7000  

RSR9
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR9 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 146 N96817948

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
868 RSR9 1.000K 1.000K 2 R 1 146 0 1.100K 0.900K 1.010K 0.0007 44.445 39.048 1.1000 0.9000  

RSR934
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR934 B3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 261 S_GPP_D11

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1032 RSR934 8.200K 8.200K 2 R 1 261 0 9.020K 7.380K 8.120K 0.0034 79.589 71.376 9.0200 7.3800  

RSR99
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR99 A2 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 72 O_KBRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1034 RSR99 8.200K 8.200K 2 R 2 72 0 9.020K 7.380K 8.140K 0.0056 49.132 45.528 9.0200 7.3800  

RUR700
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR700 B4 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 364 N03812

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
798 RUR700 470.00 470.00 2 R 797 364 0 658.00 282.00 475.17 0.1468 426.81 415.07 658.00 282.00  

RUR702
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR702 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 363 P_5V_USB_Q2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
921 RUR702 4.700K 4.700K 2 R 1 363 383 5.170K 4.230K 4.740K 0.0010 155.11 140.86 5.1700 4.2300  

RUR703
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR703 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 362 P_5V_USB_Q3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
922 RUR703 4.700K 4.700K 2 R 1 362 383 5.170K 4.230K 4.740K 0.0028 56.301 51.761 5.1700 4.2300  

RUR730
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR730 A4 T 2 2 100.0  

Pin Nail Net Name
1 524 O_PWROK
2 327 P_USBPWR_SW

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1071 RUR730 10.00K 10.00K 2 R 524 327 0 11.00K 9.00K 10.13K 0.0049 68.408 59.442 11.000 9.0000  

RUR750
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR750 C4 T 2 2 100.0  

Pin Nail Net Name
1 797 +5VSB_ATX
2 791 N16717470

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1118 RUR750 100.00K 100.00K 2 R 797 791 376 110.00K 90.00K 98.16K 0.6251 5.3330 4.3510 110.00 90.000  

RUR751
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR751 B4 T 2 2 100.0  

Pin Nail Net Name
1 373 N75707997
2 374 N16718199

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1119 RUR751 100.00K 100.00K 2 R 374 373 376 110.00K 90.00K 101.53K 0.0930 35.843 30.344 110.00 90.000  

RUR752
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR752 B4 T 2 2 100.0  

Pin Nail Net Name
1 375 N16728729
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1039 RUR752 8.200K 8.200K 2 R 3 375 1 9.020K 7.380K 8.290K 0.0049 55.428 49.165 9.0200 7.3800  

RUR753
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR753 B4 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 375 N16728729

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1040 RUR753 8.200K 8.200K 2 R 1 375 3 9.020K 7.380K 8.260K 0.0071 38.583 35.541 9.0200 7.3800  

RUR754
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR754 B4 T 2 2 100.0  

Pin Nail Net Name
1 374 N16718199
2 382 N16726466

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
871 RUR754 1.000K 1.000K 2 R 374 382 0 1.100K 0.900K 1.010K 0.0006 55.552 48.917 1.1000 0.9000  

RUR755
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR755 B4 T 2 2 100.0  

Pin Nail Net Name
1 376 P_5VSB_USB_GATE_10_1
2 791 N16717470

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
872 RUR755 1.000K 1.000K 2 R 376 791 0 1.100K 0.900K 1.000K 0.0006 52.450 50.181 1.1000 0.9000  

RUR756
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR756 B4 T 2 2 100.0  

Pin Nail Net Name
1 339 N16728809
2 427 S_SLP_S3_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1042 RUR756 8.200K 8.200K 2 R 427 339 0 9.020K 7.380K 8.280K 0.0037 74.181 66.801 9.0200 7.3800  

RUR757
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR757 F1 T 2 2 100.0  

Pin Nail Net Name
1 295 S_USB_OC_910
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1043 RUR757 8.200K 8.200K 2 R 1 295 1347 9.020K 7.380K 8.110K 0.0049 55.814 49.849 9.0200 7.3800  

RUR758
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR758 A2 T 2 2 100.0  

Pin Nail Net Name
1 395 S_USB_OC_1112
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1044 RUR758 8.200K 8.200K 2 R 1 395 109 9.020K 7.380K 8.270K 0.0059 46.670 42.770 9.0200 7.3800  

RUR759
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR759 C1 T 2 2 100.0  

Pin Nail Net Name
1 642 S_USB_OC_78
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1045 RUR759 8.200K 8.200K 2 R 1 642 624 9.020K 7.380K 8.240K 0.0101 27.158 25.717 9.0200 7.3800  

RUR760
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR760 F1 T 2 2 100.0  

Pin Nail Net Name
1 295 S_USB_OC_910
2 1347 +5V_USB_P910

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
924 RUR760 4.700K 4.700K 2 R 1347 295 1 5.170K 4.230K 4.760K 0.0016 98.563 86.067 5.1700 4.2300  

RUR761
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR761 A2 T 2 2 100.0  

Pin Nail Net Name
1 395 S_USB_OC_1112
2 109 +5V_USB_P1112

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
925 RUR761 4.700K 4.700K 2 R 109 395 1 5.170K 4.230K 4.750K 0.0021 75.288 67.101 5.1700 4.2300  

RUR762
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR762 C1 T 2 2 100.0  

Pin Nail Net Name
1 642 S_USB_OC_78
2 624 +5V_USB_P78

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
926 RUR762 4.700K 4.700K 2 R 624 642 1 5.170K 4.230K 4.730K 0.0011 139.54 129.34 5.1700 4.2300  

RUR763
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR763 A4 T 2 2 100.0  

Pin Nail Net Name
1 297 S_USB3_OC_12
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1048 RUR763 8.200K 8.200K 2 R 1 297 122 9.020K 7.380K 8.270K 0.0057 48.264 44.164 9.0200 7.3800  

RUR764
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR764 D1 T 2 2 100.0  

Pin Nail Net Name
1 656 S_USB3_OC_34
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1049 RUR764 8.200K 8.200K 2 R 1 656 991 9.020K 7.380K 8.260K 0.0065 42.126 39.034 9.0200 7.3800  

RUR765
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR765 D1 T 2 2 100.0  

Pin Nail Net Name
1 655 S_USB3_OC_56
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1050 RUR765 8.200K 8.200K 2 R 1 655 990 9.020K 7.380K 8.270K 0.0039 70.721 64.438 9.0200 7.3800  

RUR766
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR766 A4 T 2 2 100.0  

Pin Nail Net Name
1 297 S_USB3_OC_12
2 122 +5V_USB3_P12

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
927 RUR766 4.700K 4.700K 2 R 122 297 1 5.170K 4.230K 4.740K 0.0018 87.910 80.629 5.1700 4.2300  

RUR767
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR767 D1 T 2 2 100.0  

Pin Nail Net Name
1 656 S_USB3_OC_34
2 991 +5V_USB3_P34

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
928 RUR767 4.700K 4.700K 2 R 991 656 1 5.170K 4.230K 4.750K 0.0026 59.213 52.491 5.1700 4.2300  

RUR768
Device Loc Side Total Pin Tested Coverage (%) Comment
RUR768 D1 T 2 2 100.0  

Pin Nail Net Name
1 655 S_USB3_OC_56
2 990 +5V_USB3_P56

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
929 RUR768 4.700K 4.700K 2 R 990 655 1 5.170K 4.230K 4.750K 0.0022 71.289 63.905 5.1700 4.2300