Jumper Tested Devices

RL1R16 RL1R83 RL1R89 LPL101 LPL111 LPL121 LPL131 LPL141 LPL201 LPL202
LPL504 LPL511 LPL703 LPL704 LPL706 LD3F2 JAAFP LAGL1 LAGL3 LAGL4
RAGR252 LBF4 JCHAFAN JCLRTC JCOM JCPUFAN JEATX12V JEATXPWR JFPANEL LGF1
JLANSB78 RO1R100 RO1R104 RO1R110 RO1R123 RO1R143 RO1R148 RO1R159 RO1R197 RO1R98
RPR102 RPR114 RPR116 RPR120 RPR124 RPR126 RPR144 RPR160 RPR165 RPR166
RPR167 RPR170 RPR171 RPR173 RPR174 RPR175 RPR176 RPR177 RPR178 RPR179
RPR180 RPR183 RPR184 RPR185 RPR188 RPR190 RPR192 RPR193 RPR194 RPR206
RPR208 RPR209 RPR211 RPR212 RPR213 RPR214 RPR215 RPR219 RPR232 RPR304
RPR532 RPR534 RPR536 RPR538 RPR539 RPR543 RPR570 RPR623 RPR720 RPR737
RPR757 RPR758 RPR761 RPR763 RPR765 RPR766 RPR819 JSPDIFUT JSPEAKER RSR130
RSR132 RSR153 RSR154 RSR155 RSR156 RSR1623 RSR1640 RSR2000 RSR240 RSR241
RSR56 RSR632 RSR67 RSR7 RSR80 RSR81 JTPM LUF31 LUF32 LUF33
LUF4 LUF5 LUF6 JUSB1112 JUSB312          

RL1R16
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R16 B1 T 2 2 100.0  

Pin Nail Net Name
1 584 CLKREQ__LAN1
2 645 CLKREQ__LAN1_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
657 RL1R16 2.000 1.000 0 J 584 645 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RL1R83
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R83 B1 T 2 2 100.0  

Pin Nail Net Name
1 649 S_WAKE__LAN1
2 565 LAN_SIO_WAKE_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
665 RL1R83 2.000 1.000 0 J 649 565 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RL1R89
Device Loc Side Total Pin Tested Coverage (%) Comment
RL1R89 C1 T 2 2 100.0  

Pin Nail Net Name
1 651 +3VSB_LAN1
2 399 +3VSB_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
667 RL1R89 2.000 1.000 0 J 651 399 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL101
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL101 F1 T 2 2 100.0  

Pin Nail Net Name
1 1339 +12V_CPU
2 1325 P_VCORE_L+12V_S

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1900 LPL101 1.000 1.000 0 J 1339 1325 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL111
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL111 F2 T 2 2 100.0  

Pin Nail Net Name
1 1331 P_VCORE_PHASE1_20
2 948 VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1901 LPL111 1.000 1.000 0 J 1331 948 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL121
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL121 E2 T 2 2 100.0  

Pin Nail Net Name
1 1024 P_VCORE_PHASE2_20
2 948 VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1902 LPL121 1.000 1.000 0 J 1024 948 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL131
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL131 D2 T 2 2 100.0  

Pin Nail Net Name
1 1023 P_VCORE_PHASE3_20
2 948 VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1903 LPL131 1.000 1.000 0 J 1023 948 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL141
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL141 D2 T 2 2 100.0  

Pin Nail Net Name
1 949 P_VCORE_PHASE4_20
2 948 VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1904 LPL141 1.000 1.000 0 J 949 948 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL201
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL201 F3 T 2 2 100.0  

Pin Nail Net Name
1 1308 P_GT_PHASE1_20
2 1043 VCCGT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1905 LPL201 1.000 1.000 0 J 1308 1043 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL202
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL202 F2 T 2 2 100.0  

Pin Nail Net Name
1 1323 P_GT_PHASE2_20
2 1043 VCCGT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1906 LPL202 1.000 1.000 0 J 1323 1043 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL504
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL504 F4 T 2 2 100.0  

Pin Nail Net Name
1 1178 +5VDUAL
2 1150 P_VDDQ_REGIN_S

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1907 LPL504 1.000 1.000 0 J 1178 1150 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL511
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL511 E4 T 2 2 100.0  

Pin Nail Net Name
1 1147 P_VDDQ_PHASE_20
2 1148 VDDQ

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1908 LPL511 1.000 1.000 0 J 1147 1148 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL703
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL703 B4 T 2 2 100.0  

Pin Nail Net Name
1 398 P_+1_0V_A_SW_20
2 449 +1_0V_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1909 LPL703 1.000 1.000 0 J 398 449 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL704
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL704 D2 T 2 2 100.0  

Pin Nail Net Name
1 950 P_VCCSA_PHASE_20
2 946 VCCIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1910 LPL704 1.000 1.000 0 J 950 946 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LPL706
Device Loc Side Total Pin Tested Coverage (%) Comment
LPL706 B4 T 2 2 100.0  

Pin Nail Net Name
1 405 +5VSB
2 387 P_1_0A_L+5VSB_S

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1911 LPL706 1.000 1.000 0 J 405 387 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LD3F2
Device Loc Side Total Pin Tested Coverage (%) Comment
LD3F2 C4 T 2 2 100.0  

Pin Nail Net Name
1 771 VDDSPD
2 793 +3V_ATX

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1896 LD3F2 1.000 1.000 0 J 771 793 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

JAAFP
Device Loc Side Total Pin Tested Coverage (%) Comment
JAAFP A1 T 9 1 11.1  

Pin Nail Net Name
1 38 A_FMIC1_L
2 628 A_GND
3 58 A_FMIC1_R
4 57 NC_1626
5 59 A_HPOUT_R
6 56 A_JD_FMIC1
7 60 A_JD_FRONT
8 61 A_HPOUT_L
9 62 A_JD_HPOUT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
22 JAAFP_1 1.000 1.000 0 J 1409 38 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
91 JAAFP_1_2 4.000 4.000 0 J 38 628 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
221 JAAFP_2_3 4.000 4.000 0 J 628 58 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
222 JAAFP_3_4 4.000 4.000 0 J 58 57 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
223 JAAFP_4_5 4.000 4.000 0 J 57 59 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
224 JAAFP_5_6 4.000 4.000 0 J 59 56 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
225 JAAFP_6_7 4.000 4.000 0 J 56 60 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
226 JAAFP_7_8 4.000 4.000 0 J 60 61 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
227 JAAFP_8_9 4.000 4.000 0 J 61 62 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
228 JAAFP_9_1 4.000 4.000 0 J 38 62 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  

LAGL1
Device Loc Side Total Pin Tested Coverage (%) Comment
LAGL1 A1 T 2 2 100.0  

Pin Nail Net Name
1 405 +5VSB
2 53 +5VA_IN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1882 LAGL1 1.000 1.000 0 J 405 53 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LAGL3
Device Loc Side Total Pin Tested Coverage (%) Comment
LAGL3 A1 T 2 2 100.0  

Pin Nail Net Name
1 4 +12V
2 25 +12VA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1883 LAGL3 1.000 1.000 0 J 4 25 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LAGL4
Device Loc Side Total Pin Tested Coverage (%) Comment
LAGL4 A1 T 2 2 100.0  

Pin Nail Net Name
1 5 -12V
2 27 -12VA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1884 LAGL4 1.000 1.000 0 J 5 27 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RAGR252
Device Loc Side Total Pin Tested Coverage (%) Comment
RAGR252 A1 T 2 2 100.0  

Pin Nail Net Name
1 67 MUTE_POP
2 50 MUTE_POP_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
669 RAGR252 2.000 1.000 0 J 67 50 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LBF4
Device Loc Side Total Pin Tested Coverage (%) Comment
LBF4 F1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 1342 +5V_ZPS2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1895 LBF4 1.000 1.000 0 J 107 1342 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

JCHAFAN
Device Loc Side Total Pin Tested Coverage (%) Comment
JCHAFAN C2 T 5 4 80.0 No Test Nail

Pin Nail Net Name
1 668 O_CHAFAN_PWM_Q
2 669 O_CHAFANIN1_R
3 4 +12V
4 1 GND
5 0 NC_1643

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
8 JCHAFAN 1.000 1.000 0 J 1439 1440 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
38 JCHAFAN_1 1.000 1.000 0 J 1425 668 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
39 JCHAFAN_2 1.000 1.000 0 J 1426 669 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
40 JCHAFAN_3 1.000 1.000 0 J 1427 4 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
41 JCHAFAN_4 1.000 1.000 0 J 1428 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
76 JCHAFAN_1_2 4.000 4.000 0 J 668 669 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
77 JCHAFAN_2_3 4.000 4.000 0 J 669 4 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
78 JCHAFAN_3_4/J 4.000 4.000 0 J 4 1 0 4.400 3.600 NA NA NA NA NA NA  
79 JCHAFAN/NP_4 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
80 JCHAFAN/NP_5 4.000 4.000 0 J 668 0 0 4.400 3.600 NA NA NA NA NA NA  

JCLRTC
Device Loc Side Total Pin Tested Coverage (%) Comment
JCLRTC A2 T 2 2 100.0  

Pin Nail Net Name
1 103 +3V_BAT_RTC
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
28 JCLRTC_1 1.000 1.000 0 J 1415 103 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
29 JCLRTC_2 1.000 1.000 0 J 1416 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
81 JCLRTC 4.000 4.000 0 J 103 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  

JCOM
Device Loc Side Total Pin Tested Coverage (%) Comment
JCOM C2 T 9 1 11.1  

Pin Nail Net Name
1 660 LS_COM1_DCD1_
2 667 LS_COM1_RXD1
3 661 LS_COM1_TXD1
4 666 LS_COM1_DTR1_
5 1 GND
6 665 LS_COM1_DSR1_
7 662 LS_COM1_RTS1_
8 664 LS_COM1_CTS1_
9 663 LS_COM1_RI1_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
37 JCOM_1 1.000 1.000 0 J 1424 660 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
82 JCOM_1_2 4.000 4.000 0 J 660 667 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
83 JCOM_2_3 4.000 4.000 0 J 667 661 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
84 JCOM_3_4 4.000 4.000 0 J 661 666 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
85 JCOM_4_5 4.000 4.000 0 J 666 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
86 JCOM_5_6 4.000 4.000 0 J 1 665 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
87 JCOM_6_7 4.000 4.000 0 J 665 662 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
88 JCOM_7_8 4.000 4.000 0 J 662 664 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
89 JCOM_8_9 4.000 4.000 0 J 664 663 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
90 JCOM_9_1 4.000 4.000 0 J 660 663 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  

JCPUFAN
Device Loc Side Total Pin Tested Coverage (%) Comment
JCPUFAN F3 T 5 4 80.0 No Test Nail

Pin Nail Net Name
1 1305 O_CPUFAN_PWM_Q
2 1304 O_CPUFANIN_R
3 4 +12V
4 1 GND
5 0 NC_1644

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
9 JCPUFAN 1.000 1.000 0 J 1441 1442 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
43 JCPUFAN_1 1.000 1.000 0 J 1430 1305 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
44 JCPUFAN_2 1.000 1.000 0 J 1431 1304 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
45 JCPUFAN_3 1.000 1.000 0 J 1432 4 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
46 JCPUFAN_4 1.000 1.000 0 J 1433 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
92 JCPUFAN_1_2 4.000 4.000 0 J 1305 1304 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
93 JCPUFAN_2_3 4.000 4.000 0 J 1304 4 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
94 JCPUFAN_3_4/J 4.000 4.000 0 J 4 1 0 4.400 3.600 NA NA NA NA NA NA  
95 JCPUFAN/NP_4 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
96 JCPUFAN/NP_5 4.000 4.000 0 J 1305 0 0 4.400 3.600 NA NA NA NA NA NA  

JEATX12V
Device Loc Side Total Pin Tested Coverage (%) Comment
JEATX12V F1 T 10 4 40.0 No Test Nail

Pin Nail Net Name
1 1 GND
2 1 GND
3 1 GND
4 1 GND
5 1339 +12V_CPU
6 1339 +12V_CPU
7 1339 +12V_CPU
8 1339 +12V_CPU
9 0 NC_1553
10 0 NC_1554

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
42 JEATX12V_1 1.000 1.000 0 J 1429 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
129 JEATX12V_1_2/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
130 JEATX12V_2_3/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
131 JEATX12V_3_4/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
132 JEATX12V_4_5/ 4.000 4.000 0 J 1 1339 0 4.400 3.600 NA NA NA NA NA NA  
133 JEATX12V_5_6/ 4.000 4.000 0 J 1339 0 0 4.400 3.600 NA NA NA NA NA NA  
134 JEATX12V_6_7/ 4.000 4.000 0 J 1339 0 0 4.400 3.600 NA NA NA NA NA NA  
135 JEATX12V_7_8/ 4.000 4.000 0 J 1339 0 0 4.400 3.600 NA NA NA NA NA NA  
136 JEATX12V/NP_ 4.000 4.000 0 J 1339 0 0 4.400 3.600 NA NA NA NA NA NA  
137 JEATX12V/NP_ 4.000 4.000 0 J 0 0 0 4.400 3.600 NA NA NA NA NA NA  
138 JEATX12V/NP_ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  

JEATXPWR
Device Loc Side Total Pin Tested Coverage (%) Comment
JEATXPWR D4 T 26 4 15.4 No Test Nail

Pin Nail Net Name
1 793 +3V_ATX
2 793 +3V_ATX
3 1 GND
4 3 +5V
5 1 GND
6 3 +5V
7 1 GND
8 796 P_PWROK_PS
9 797 +5VSB_ATX
10 4 +12V
11 4 +12V
12 793 +3V_ATX
13 793 +3V_ATX
14 5 -12V
15 1 GND
16 794 ATX_PSON__R
17 1 GND
18 1 GND
19 1 GND
20 795 -5V
21 3 +5V
22 3 +5V
23 3 +5V
24 1 GND
25 0 NC_1645
26 0 NC_1646

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
36 JEATXPWR_1 1.000 1.000 0 J 1423 793 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
139 JEATXPWR_1_2/ 4.000 4.000 0 J 793 0 0 4.400 3.600 NA NA NA NA NA NA  
140 JEATXPWR_2_3/ 4.000 4.000 0 J 793 1 0 4.400 3.600 NA NA NA NA NA NA  
141 JEATXPWR_3_4/ 4.000 4.000 0 J 1 3 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
142 JEATXPWR_4_5/ 4.000 4.000 0 J 3 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
143 JEATXPWR_5_6/ 4.000 4.000 0 J 1 3 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
144 JEATXPWR_6_7/ 4.000 4.000 0 J 3 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
145 JEATXPWR_7_8 4.000 4.000 0 J 1 796 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
146 JEATXPWR_8_9 4.000 4.000 0 J 796 797 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
147 JEATXPWR_9_1/ 4.000 4.000 0 J 797 4 0 4.400 3.600 NA NA NA NA NA NA  
148 JEATXPWR_10_/ 4.000 4.000 0 J 4 0 0 4.400 3.600 NA NA NA NA NA NA  
149 JEATXPWR_11_ 4.000 4.000 0 J 4 793 0 4.400 3.600 NA NA NA NA NA NA  
150 JEATXPWR_12_/ 4.000 4.000 0 J 793 0 0 4.400 3.600 NA NA NA NA NA NA  
151 JEATXPWR_13_ 4.000 4.000 0 J 793 5 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
152 JEATXPWR_14_ 4.000 4.000 0 J 5 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
153 JEATXPWR_15_/ 4.000 4.000 0 J 1 794 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
154 JEATXPWR_16_/ 4.000 4.000 0 J 794 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
155 JEATXPWR_17_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
156 JEATXPWR_18_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
157 JEATXPWR_19_ 4.000 4.000 0 J 1 795 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
158 JEATXPWR_20_ 4.000 4.000 0 J 795 3 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
159 JEATXPWR_21_/ 4.000 4.000 0 J 3 0 0 4.400 3.600 NA NA NA NA NA NA  
160 JEATXPWR_22_/ 4.000 4.000 0 J 3 0 0 4.400 3.600 NA NA NA NA NA NA  
161 JEATXPWR_23_/ 4.000 4.000 0 J 3 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
162 JEATXPWR/NP_ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
163 JEATXPWR/NP_ 4.000 4.000 0 J 0 0 0 4.400 3.600 NA NA NA NA NA NA  
164 JEATXPWR/NP_ 4.000 4.000 0 J 793 0 0 4.400 3.600 NA NA NA NA NA NA  

JFPANEL
Device Loc Side Total Pin Tested Coverage (%) Comment
JFPANEL A4 T 9 1 11.1  

Pin Nail Net Name
1 334 HDLED+
2 335 PLED+
3 345 HDLED-
4 344 PLED-
5 1 GND
6 346 PWRBTN__PANEL
7 347 O_RSTCON__PR
8 1 GND
9 348 NC_1625

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
35 JFPANEL_1 1.000 1.000 0 J 1422 334 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
165 JFPANEL_1_2 4.000 4.000 0 J 334 335 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
166 JFPANEL_2_3 4.000 4.000 0 J 335 345 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
167 JFPANEL_3_4 4.000 4.000 0 J 345 344 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
168 JFPANEL_4_5 4.000 4.000 0 J 344 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
169 JFPANEL_5_6 4.000 4.000 0 J 1 346 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
170 JFPANEL_6_7 4.000 4.000 0 J 346 347 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
171 JFPANEL_7_8 4.000 4.000 0 J 347 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
172 JFPANEL_8_9 4.000 4.000 0 J 1 348 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
173 JFPANEL_9_1 4.000 4.000 0 J 334 348 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  

LGF1
Device Loc Side Total Pin Tested Coverage (%) Comment
LGF1 E1 T 2 2 100.0  

Pin Nail Net Name
1 1012 +5V_DVI_HDMI_Q
2 1005 +5V_DVI_HDMI

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1897 LGF1 1.000 1.000 0 J 1012 1005 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

JLANSB78
Device Loc Side Total Pin Tested Coverage (%) Comment
JLANSB78 C1 T 28 18 64.3  

Pin Nail Net Name
1 624 +5V_USB_P78
2 623 S_USB_PN7
3 622 S_USB_PP7
4 1 GND
5 624 +5V_USB_P78
6 625 S_USB_PN6
7 626 S_USB_PP6
8 1 GND
9 637 L1_TR_P0
10 630 L1_TR_N0
11 636 L1_TR_P1
12 631 L1_TR_P2
13 635 L1_TR_N2
14 632 L1_TR_N1
15 634 L1_TR_P3
16 633 L1_TR_N3
17 641 L1_ACTLEDP
18 640 L1_ACTLEDN
19 639 L1_LINK1000_
20 638 L1_LINK100_
21 1 GND
22 1 GND
23 1 GND
24 1 GND
25 1 GND
26 1 GND
27 1 GND
28 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
193 JLANSB78_1_2 4.000 4.000 0 J 624 623 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
194 JLANSB78_2_3 4.000 4.000 0 J 623 622 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
195 JLANSB78_3_4 4.000 4.000 0 J 622 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
196 JLANSB78_4_5/ 4.000 4.000 0 J 1 624 0 4.400 3.600 NA NA NA NA NA NA  
197 JLANSB78_5_6 4.000 4.000 0 J 624 625 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
198 JLANSB78_6_7 4.000 4.000 0 J 625 626 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
199 JLANSB78_7_8 4.000 4.000 0 J 626 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
200 JLANSB78_8_9 1.000 1.000 0 J 1 637 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
201 JLANSB78_9_1 1.000 1.000 0 J 637 630 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
202 JLANSB78_10_ 1.000 1.000 0 J 630 636 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
203 JLANSB78_11_ 1.000 1.000 0 J 636 631 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
204 JLANSB78_12_ 1.000 1.000 0 J 631 635 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
205 JLANSB78_13_ 1.000 1.000 0 J 635 632 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
206 JLANSB78_14_ 1.000 1.000 0 J 632 634 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
207 JLANSB78_15_ 1.000 1.000 0 J 634 633 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
208 JLANSB78_16_ 4.000 4.000 0 J 633 641 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
209 JLANSB78_17_ 4.000 4.000 0 J 641 640 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
210 JLANSB78_18_ 4.000 4.000 0 J 640 639 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
211 JLANSB78_19_ 4.000 4.000 0 J 639 638 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
212 JLANSB78_20_ 4.000 4.000 0 J 638 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
213 JLANSB78_21_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
214 JLANSB78_22_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
215 JLANSB78_23_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
216 JLANSB78_24_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
217 JLANSB78_25_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
218 JLANSB78_26_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
219 JLANSB78_27_/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
220 JLANSB78_28_/ 4.000 4.000 0 J 624 1 0 4.400 3.600 NA NA NA NA NA NA  

RO1R100
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R100 B1 T 2 2 100.0  

Pin Nail Net Name
1 1063 H_SKTOCC_
2 608 O_5V_IN_2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
652 RO1R100 2.000 1.000 0 J 1063 608 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RO1R104
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R104 B1 T 2 2 100.0  

Pin Nail Net Name
1 71 +3V_BAT
2 596 +3V_BAT_1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
653 RO1R104 2.000 1.000 0 J 71 596 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RO1R110
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R110 B1 T 2 2 100.0  

Pin Nail Net Name
1 598 O_12V_IN_2
2 130 O_RSMRST_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
654 RO1R110 2.000 1.000 0 J 598 130 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RO1R123
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R123 B1 T 2 2 100.0  

Pin Nail Net Name
1 399 +3VSB_ATX
2 605 +AVCC_SIO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
655 RO1R123 2.000 1.000 0 J 399 605 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RO1R143
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R143 B1 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 600 +3V_O1P1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
658 RO1R143 2.000 1.000 0 J 2 600 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RO1R148
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R148 B1 T 2 2 100.0  

Pin Nail Net Name
1 603 O_PLED
2 599 O1_PIN42

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
660 RO1R148 2.000 1.000 0 J 603 599 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RO1R159
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R159 B1 T 2 2 100.0  

Pin Nail Net Name
1 426 VCCST_VCCSFR
2 614 +VTT_O1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
661 RO1R159 2.000 1.000 0 J 426 614 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RO1R197
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R197 B1 T 2 2 100.0  

Pin Nail Net Name
1 593 AUDIO_LED_PWM
2 597 +3V_BAT_2

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
663 RO1R197 2.000 1.000 0 J 593 597 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RO1R98
Device Loc Side Total Pin Tested Coverage (%) Comment
RO1R98 B1 T 2 2 100.0  

Pin Nail Net Name
1 580 O_SLP_S3__R
2 523 O_PSON__O1

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
668 RO1R98 2.000 1.000 0 J 580 523 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR102
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR102 F3 T 2 2 100.0  

Pin Nail Net Name
1 1252 P_VCORE_VCC5_20
2 3 +5V

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
693 RPR102 2.200 1.000 0 J 1252 3 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR114
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR114 F3 T 2 2 100.0  

Pin Nail Net Name
1 1261 P_GT_CSREFA_10
2 1322 P_GT_CSN2A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
702 RPR114 10.00 1.000 0 J 1261 1322 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR116
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR116 F3 T 2 2 100.0  

Pin Nail Net Name
1 1268 P_VCORE_CSREF_10
2 1288 P_VCORE_CSN2_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
703 RPR116 10.00 1.000 0 J 1268 1288 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR120
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR120 F3 T 2 2 100.0  

Pin Nail Net Name
1 1268 P_VCORE_CSREF_10
2 1320 P_VCORE_CSN1_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
704 RPR120 10.00 1.000 0 J 1268 1320 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR124
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR124 F3 T 2 2 100.0  

Pin Nail Net Name
1 1261 P_GT_CSREFA_10
2 1301 P_GT_CSN1A_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
705 RPR124 10.00 1.000 0 J 1261 1301 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR126
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR126 F3 T 2 2 100.0  

Pin Nail Net Name
1 1268 P_VCORE_CSREF_10
2 1269 P_VCORE_CSN3_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
706 RPR126 10.00 1.000 0 J 1268 1269 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR144
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR144 F3 T 2 2 100.0  

Pin Nail Net Name
1 1268 P_VCORE_CSREF_10
2 1286 P_VCORE_CSN4_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
707 RPR144 10.00 1.000 0 J 1268 1286 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR160
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR160 E2 T 2 2 100.0  

Pin Nail Net Name
1 1038 P_DRIVER2_VCC_20
2 1036 P_VCORE_VCC2_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
694 RPR160 2.200 1.000 0 J 1038 1036 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR165
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR165 E2 T 2 2 100.0  

Pin Nail Net Name
1 1035 P_VCORE_BST2_20
2 1034 P_VCORE_BST2_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
436 RPR165 1.000 1.000 0 J 1035 1034 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR166
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR166 E1 T 2 2 100.0  

Pin Nail Net Name
1 1016 P_VCORE_BST3_20
2 1014 P_VCORE_BST3_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
437 RPR166 1.000 1.000 0 J 1016 1014 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR167
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR167 E2 T 2 2 100.0  

Pin Nail Net Name
1 1032 P_DRIVER3_VCC_20
2 1028 P_VCORE_VCC3_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
695 RPR167 2.200 1.000 0 J 1032 1028 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR170
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR170 F2 T 2 2 100.0  

Pin Nail Net Name
1 1333 P_DRIVER1_VCC_20
2 1332 P_VCORE_VCC1_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
696 RPR170 2.200 1.000 0 J 1333 1332 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR171
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR171 F2 T 2 2 100.0  

Pin Nail Net Name
1 1335 P_VCORE_BST1_20
2 1336 P_VCORE_BST1_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
438 RPR171 1.000 1.000 0 J 1335 1336 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR173
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR173 E2 T 2 2 100.0  

Pin Nail Net Name
1 1031 P_DRIVER4_VCC_20
2 1029 P_VCORE_VCC4_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
692 RPR173 2.200 1.000 0 J 1031 1029 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR174
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR174 F2 T 2 2 100.0  

Pin Nail Net Name
1 1327 P_VCORE_HG1_20
2 1328 P_VCORE_R_HG1_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
638 RPR174 2.000 1.000 0 J 1327 1328 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR175
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR175 E2 T 2 2 100.0  

Pin Nail Net Name
1 1033 P_VCORE_HG2_20
2 1017 P_VCORE_R_HG2_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
639 RPR175 2.000 1.000 0 J 1033 1017 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR176
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR176 E2 T 2 2 100.0  

Pin Nail Net Name
1 1018 P_VCORE_HG3_20
2 1020 P_VCORE_R_HG3_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
640 RPR176 2.000 1.000 0 J 1018 1020 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR177
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR177 F2 T 2 2 100.0  

Pin Nail Net Name
1 1337 P_VCORE_PH1_SNU_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
439 RPR177 1.000 1.000 0 J 1337 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR178
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR178 E2 T 2 2 100.0  

Pin Nail Net Name
1 1019 P_VCORE_PH2_SNU_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
440 RPR178 1.000 1.000 0 J 1019 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR179
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR179 D2 T 2 2 100.0  

Pin Nail Net Name
1 1021 P_VCORE_PH3_SNU_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
441 RPR179 1.000 1.000 0 J 1021 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR180
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR180 D2 T 2 2 100.0  

Pin Nail Net Name
1 962 P_VCORE_PH4_SNU_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
442 RPR180 1.000 1.000 0 J 962 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR183
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR183 F4 T 2 2 100.0  

Pin Nail Net Name
1 1225 P_+VCCIO_PG_10
2 1236 P_VCORE_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
641 RPR183 2.000 1.000 0 J 1225 1236 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR184
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR184 F3 T 2 2 100.0  

Pin Nail Net Name
1 1273 H_SVID_DATA
2 1249 P_SVID_DATA

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
708 RPR184 10.00 1.000 0 J 1273 1249 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR185
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR185 F3 T 2 2 100.0  

Pin Nail Net Name
1 1278 H_SVID_ALERT_
2 1250 P_SVID_ALERT_

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
642 RPR185 2.000 1.000 0 J 1278 1250 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR188
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR188 F3 T 2 2 100.0  

Pin Nail Net Name
1 1279 P_VCORE_VRHOT__R_10
2 1254 P_VCORE_VRHOT__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
643 RPR188 2.000 1.000 0 J 1279 1254 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR190
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR190 F3 T 2 2 100.0  

Pin Nail Net Name
1 1237 P_SMB_CLK_4
2 712 S_SMBCLK_MAIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
644 RPR190 2.000 1.000 0 J 1237 712 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR192
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR192 F3 T 2 2 100.0  

Pin Nail Net Name
1 1232 P_SMB_DATA_4
2 770 S_SMBDATA_MAIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
645 RPR192 2.000 1.000 0 J 1232 770 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR193
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR193 D2 T 2 2 100.0  

Pin Nail Net Name
1 1022 P_VCORE_HG4_20
2 960 P_VCORE_R_HG4_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
646 RPR193 2.000 1.000 0 J 1022 960 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR194
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR194 E1 T 2 2 100.0  

Pin Nail Net Name
1 1015 P_VCORE_BST4_20
2 1013 P_VCORE_BST4_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
445 RPR194 1.000 1.000 0 J 1015 1013 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR206
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR206 F3 T 2 2 100.0  

Pin Nail Net Name
1 1299 P_GT_DRIVER_VCC_20
2 1290 P_GT_VCC1_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
690 RPR206 2.200 1.000 0 J 1299 1290 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR208
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR208 F3 T 2 2 100.0  

Pin Nail Net Name
1 1297 P_GT_BST1_20
2 1295 P_GT_BST1_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
451 RPR208 1.000 1.000 0 J 1297 1295 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR209
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR209 F2 T 2 2 100.0  

Pin Nail Net Name
1 1303 P_GT_DRIVER2_VCC_20
2 1310 P_GT_VCC2_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
691 RPR209 2.200 1.000 0 J 1303 1310 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR211
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR211 F2 T 2 2 100.0  

Pin Nail Net Name
1 1312 P_GT_BST2_20
2 1313 P_GT_BST2_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
452 RPR211 1.000 1.000 0 J 1312 1313 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR212
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR212 F3 T 2 2 100.0  

Pin Nail Net Name
1 1291 P_GT_R_HG1_20
2 1296 P_GT_R_HG1_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
647 RPR212 2.000 1.000 0 J 1291 1296 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR213
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR213 F2 T 2 2 100.0  

Pin Nail Net Name
1 1311 P_GT_R_HG2_20
2 1316 P_GT_R_HG2_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
648 RPR213 2.000 1.000 0 J 1311 1316 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR214
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR214 F2 T 2 2 100.0  

Pin Nail Net Name
1 1306 P_GT_PH1_SNU_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
453 RPR214 1.000 1.000 0 J 1306 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR215
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR215 F2 T 2 2 100.0  

Pin Nail Net Name
1 1324 P_GT_PH2_SNU_10
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
454 RPR215 1.000 1.000 0 J 1324 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR219
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR219 F3 T 2 2 100.0  

Pin Nail Net Name
1 1293 P_GT_BOOT_R
2 1062 P_CPU_GND_GT

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
649 RPR219 2.000 1.000 0 J 1293 1062 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR232
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR232 F3 T 2 2 100.0  

Pin Nail Net Name
1 1285 P_VCORE_BOOT_R
2 1287 P_CPU_GND_VCORE

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
650 RPR232 2.000 1.000 0 J 1285 1287 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR304
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR304 F4 T 2 2 100.0  

Pin Nail Net Name
1 788 P_+VCCIO_EN_10
2 1222 P_+VDDQ_PG_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
651 RPR304 2.000 1.000 0 J 788 1222 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR532
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR532 E4 T 2 2 100.0  

Pin Nail Net Name
1 1145 P_VDDQ_SNB
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
487 RPR532 1.000 1.000 0 J 1145 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR534
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR534 F4 T 2 2 100.0  

Pin Nail Net Name
1 1175 P_VDDQ_BOOT_20
2 1174 P_VDDQ_BOOT_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
488 RPR534 1.000 1.000 0 J 1175 1174 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR536
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR536 F4 T 2 2 100.0  

Pin Nail Net Name
1 1177 P_VDDQ_VCC_20
2 1183 P_VDDQ_VCC_P_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
687 RPR536 2.200 1.000 0 J 1177 1183 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR538
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR538 F4 T 2 2 100.0  

Pin Nail Net Name
1 1158 P_VDDQ_FB_C_10
2 1168 P_VDDQ_FB_SHORTPIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
698 RPR538 10.00 1.000 0 J 1158 1168 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR539
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR539 E4 T 2 2 100.0  

Pin Nail Net Name
1 1149 P_VDDQ_UGATE_M_20
2 1176 P_VDDQ_UGATE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
656 RPR539 2.000 1.000 0 J 1149 1176 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR543
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR543 C4 T 2 2 100.0  

Pin Nail Net Name
1 2 +3V
2 709 P_VTT_DDR_CTRL_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
699 RPR543 10.00 1.000 0 J 2 709 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR570
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR570 B3 T 2 2 100.0  

Pin Nail Net Name
1 406 DDR_VTT_CNTL_B_R_10
2 1220 H_DDR_VTT_CNTL

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
659 RPR570 2.000 1.000 0 J 406 1220 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR623
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR623 F4 T 2 2 100.0  

Pin Nail Net Name
1 581 O_3VSBSW_
2 1151 N16880461

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
662 RPR623 2.000 1.000 0 J 581 1151 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR720
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR720 B4 T 2 2 100.0  

Pin Nail Net Name
1 405 +5VSB
2 402 P_+1_0V_A_LP__10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
688 RPR720 2.200 1.000 0 J 405 402 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR737
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR737 B4 T 2 2 100.0  

Pin Nail Net Name
1 391 P_+1_0V_A_BST_R_20
2 389 P_+1_0V_A_BST_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
697 RPR737 4.700 1.000 0 J 391 389 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR757
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR757 D2 T 2 2 100.0  

Pin Nail Net Name
1 963 P_VCCSA_UGATE_M_20
2 953 P_VCCSA_UGATE_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
664 RPR757 2.000 1.000 0 J 963 953 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR758
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR758 D1 T 2 2 100.0  

Pin Nail Net Name
1 968 P_VCCSA_FB_C_10
2 966 P_VCCSA_FB_SHORTPIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
700 RPR758 10.00 1.000 0 J 968 966 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR761
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR761 D2 T 2 2 100.0  

Pin Nail Net Name
1 958 P_VCCSA_VCC_20
2 1339 +12V_CPU

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
689 RPR761 2.200 1.000 0 J 958 1339 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR763
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR763 D2 T 2 2 100.0  

Pin Nail Net Name
1 964 P_VCCSA_SNB
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
510 RPR763 1.000 1.000 0 J 964 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR765
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR765 D2 T 2 2 100.0  

Pin Nail Net Name
1 954 P_VCCSA_BOOT_20
2 952 P_VCCSA_BOOT_R_20

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
511 RPR765 1.000 1.000 0 J 954 952 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR766
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR766 D1 T 2 2 100.0  

Pin Nail Net Name
1 951 P_VCCSA_FB_R_SHORTPIN
2 966 P_VCCSA_FB_SHORTPIN

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
701 RPR766 10.00 1.000 0 J 951 966 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RPR819
Device Loc Side Total Pin Tested Coverage (%) Comment
RPR819 F3 T 2 2 100.0  

Pin Nail Net Name
1 788 P_+VCCIO_EN_10
2 1229 P_+12V_3V_EN_10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
666 RPR819 2.000 1.000 0 J 788 1229 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

JSPDIFUT
Device Loc Side Total Pin Tested Coverage (%) Comment
JSPDIFUT A2 T 3 3 100.0  

Pin Nail Net Name
1 3 +5V
2 80 A_SPDIFO_HEADER
3 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
23 JSPDIFUT_1 1.000 1.000 0 J 1410 3 0 1.100 0.900 1.600 1.3416 0.0250 0.1240 1.1000 0.9000  
24 JSPDIFUT_2 1.000 1.000 0 J 1411 80 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
25 JSPDIFUT_3 1.000 1.000 0 J 1412 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
278 JSPDIFUT_1_2 4.000 4.000 0 J 3 80 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
279 JSPDIFUT_2_3 4.000 4.000 0 J 80 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
280 JSPDIFUT_3_1/ 4.000 4.000 0 J 3 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  

JSPEAKER
Device Loc Side Total Pin Tested Coverage (%) Comment
JSPEAKER A4 T 4 4 100.0  

Pin Nail Net Name
1 322 +5V_SPKO
2 1 GND
3 1 GND
4 333 SPKO

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
31 JSPEAKER_1 1.000 1.000 0 J 1418 322 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
32 JSPEAKER_2 1.000 1.000 0 J 1419 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
33 JSPEAKER_3 1.000 1.000 0 J 1420 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
34 JSPEAKER_4 1.000 1.000 0 J 1421 333 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
281 JSPEAKER_1_2 4.000 4.000 0 J 322 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
282 JSPEAKER_2_3/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
283 JSPEAKER_3_4 4.000 4.000 0 J 1 333 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
284 JSPEAKER_4_1 4.000 4.000 0 J 322 333 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  

RSR130
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR130 A4 T 2 2 100.0  

Pin Nail Net Name
1 325 N97614572
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
670 RSR130 2.000 1.000 0 J 325 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR132
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR132 A4 T 2 2 100.0  

Pin Nail Net Name
1 384 P_VR_READY_10
2 136 S_SYSPWROK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
671 RSR132 2.000 1.000 0 J 384 136 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR153
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR153 B3 T 2 2 100.0  

Pin Nail Net Name
1 450 +1_0V_A_XCLK_BIAS
2 449 +1_0V_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
672 RSR153 2.000 1.000 0 J 450 449 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR154
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR154 A3 T 2 2 100.0  

Pin Nail Net Name
1 139 +1_0V_A_VCCAPLL
2 449 +1_0V_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
673 RSR154 2.000 1.000 0 J 139 449 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR155
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR155 B3 T 2 2 100.0  

Pin Nail Net Name
1 420 +1_0V_A_VCCAMPHYPLL
2 449 +1_0V_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
674 RSR155 2.000 1.000 0 J 420 449 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR156
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR156 B3 T 2 2 100.0  

Pin Nail Net Name
1 414 +1_0V_A_VCCMIPIPLL
2 449 +1_0V_A

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
675 RSR156 2.000 1.000 0 J 414 449 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR1623
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1623 A3 T 2 2 100.0  

Pin Nail Net Name
1 301 ME_UNLOCK
2 137 S_HD_SDOUT_R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
676 RSR1623 2.000 1.000 0 J 301 137 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR1640
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR1640 A3 T 2 2 100.0  

Pin Nail Net Name
1 271 S_PWROK
2 524 O_PWROK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
677 RSR1640 2.000 1.000 0 J 271 524 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR2000
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR2000 B3 T 2 2 100.0  

Pin Nail Net Name
1 408 O_+12V_DUMMYLOAD2
2 409 S_GPP_H14

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
678 RSR2000 2.000 1.000 0 J 408 409 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR240
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR240 A3 T 2 2 100.0  

Pin Nail Net Name
1 1 GND
2 145 CPU_VSS_AB10

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
679 RSR240 2.000 1.000 0 J 1 145 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR241
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR241 A3 T 2 2 100.0  

Pin Nail Net Name
1 143 CPU_VSS_AB11
2 1 GND

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
680 RSR241 2.000 1.000 0 J 143 1 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR56
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR56 A4 T 2 2 100.0  

Pin Nail Net Name
1 309 S_D4_RESET_
2 1095 S_D4_RESET__R

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
681 RSR56 2.000 1.000 0 J 309 1095 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR632
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR632 C2 T 2 2 100.0  

Pin Nail Net Name
1 1280 P_VCORE_VRSHDN_10
2 673 N45021399

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
682 RSR632 2.000 1.000 0 J 1280 673 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR67
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR67 A3 T 2 2 100.0  

Pin Nail Net Name
1 159 +3VSB_HDA
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
683 RSR67 2.000 1.000 0 J 159 549 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR7
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR7 A3 T 2 2 100.0  

Pin Nail Net Name
1 277 VCCPGPPD
2 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
684 RSR7 2.000 1.000 0 J 277 549 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR80
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR80 A3 T 2 2 100.0  

Pin Nail Net Name
1 130 O_RSMRST_
2 157 S_DPWROK

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
685 RSR80 2.000 1.000 0 J 130 157 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

RSR81
Device Loc Side Total Pin Tested Coverage (%) Comment
RSR81 A2 T 2 2 100.0  

Pin Nail Net Name
1 549 +3VSB
2 144 +3VSB_ADV

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
686 RSR81 2.000 1.000 0 J 549 144 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

JTPM
Device Loc Side Total Pin Tested Coverage (%) Comment
JTPM A2 T 13 1 7.7  

Pin Nail Net Name
1 89 S_LAD0
2 2 +3V
3 88 S_LAD1
4 2 +3V
5 86 S_LAD2
6 87 CK_24M_TPM
7 85 S_LAD3
8 1 GND
9 84 S_LFRAME_
10 82 S_SERIRQ
11 83 S_PLTRST_
12 81 TPM_PD_
13 549 +3VSB

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
26 JTPM_1 1.000 1.000 0 J 1413 89 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
285 JTPM_1_2 4.000 4.000 0 J 89 2 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
288 JTPM_4_5 4.000 4.000 0 J 2 86 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
289 JTPM_5_6 4.000 4.000 0 J 86 87 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
290 JTPM_6_7 4.000 4.000 0 J 87 85 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
291 JTPM_7_8 4.000 4.000 0 J 85 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
292 JTPM_8_9 4.000 4.000 0 J 1 84 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
293 JTPM_9_10 4.000 4.000 0 J 84 82 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
294 JTPM_10_11 4.000 4.000 0 J 82 83 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
295 JTPM_11_12 4.000 4.000 0 J 83 81 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
296 JTPM_12_13 4.000 4.000 0 J 81 549 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
297 JTPM_13_1 4.000 4.000 0 J 89 549 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  

LUF31
Device Loc Side Total Pin Tested Coverage (%) Comment
LUF31 A2 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 122 +5V_USB3_P12

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1920 LUF31 1.000 1.000 0 J 107 122 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LUF32
Device Loc Side Total Pin Tested Coverage (%) Comment
LUF32 D1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 991 +5V_USB3_P34

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1921 LUF32 1.000 1.000 0 J 107 991 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LUF33
Device Loc Side Total Pin Tested Coverage (%) Comment
LUF33 D1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 990 +5V_USB3_P56

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1922 LUF33 1.000 1.000 0 J 107 990 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LUF4
Device Loc Side Total Pin Tested Coverage (%) Comment
LUF4 C1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 624 +5V_USB_P78

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1923 LUF4 1.000 1.000 0 J 107 624 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LUF5
Device Loc Side Total Pin Tested Coverage (%) Comment
LUF5 F1 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 1347 +5V_USB_P910

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1924 LUF5 1.000 1.000 0 J 107 1347 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

LUF6
Device Loc Side Total Pin Tested Coverage (%) Comment
LUF6 A2 T 2 2 100.0  

Pin Nail Net Name
1 107 +5VSB_DUAL
2 109 +5V_USB_P1112

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
1925 LUF6 1.000 1.000 0 J 107 109 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  

JUSB1112
Device Loc Side Total Pin Tested Coverage (%) Comment
JUSB1112 A2 T 9 2 22.2  

Pin Nail Net Name
1 109 +5V_USB_P1112
2 109 +5V_USB_P1112
3 110 S_USB_PN11
4 108 S_USB_PN10
5 111 S_USB_PP11
6 112 S_USB_PP10
7 1 GND
8 1 GND
9 113 NC_1374

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
27 JUSB1112_1 1.000 1.000 0 J 1414 109 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
298 JUSB1112_1_2/ 4.000 4.000 0 J 109 0 0 4.400 3.600 NA NA NA NA NA NA  
299 JUSB1112_2_3 4.000 4.000 0 J 109 110 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
300 JUSB1112_3_4 4.000 4.000 0 J 110 108 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
301 JUSB1112_4_5 4.000 4.000 0 J 108 111 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
302 JUSB1112_5_6 4.000 4.000 0 J 111 112 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
303 JUSB1112_6_7 4.000 4.000 0 J 112 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
304 JUSB1112_7_8/ 4.000 4.000 0 J 1 0 0 4.400 3.600 NA NA NA NA NA NA  
305 JUSB1112_8_9 4.000 4.000 0 J 1 113 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
306 JUSB1112_9_1 4.000 4.000 0 J 109 113 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  

JUSB312
Device Loc Side Total Pin Tested Coverage (%) Comment
JUSB312 A3 T 19 2 10.5  

Pin Nail Net Name
1 122 +5V_USB3_P12
2 123 S_U3RXDN1
3 124 S_U3RXDP1
4 1 GND
5 127 S_U3TXDN1
6 172 S_U3TXDP1
7 1 GND
8 171 S_U2DN1
9 170 S_U2DP1
10 1 GND
11 176 S_U2DP2
12 175 S_U2DN2
13 1 GND
14 174 S_U3TXDP2
15 173 S_U3TXDN2
16 1 GND
17 126 S_U3RXDP2
18 125 S_U3RXDN2
19 122 +5V_USB3_P12

Step Name BOM_V EXP_V Mode Type HiN LoN G1 HVal LVal Mean StdDev Cp Cpk USL LSL Message
30 JUSB312_1 1.000 1.000 0 J 1417 122 0 1.100 0.900 1.000 0.0000 99999 99999 1.1000 0.9000  
307 JUSB312_1_2 4.000 4.000 0 J 122 123 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
308 JUSB312_2_3 4.000 4.000 0 J 123 124 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
309 JUSB312_3_4 4.000 4.000 0 J 124 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
310 JUSB312_4_5 4.000 4.000 0 J 1 127 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
311 JUSB312_5_6 4.000 4.000 0 J 127 172 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
312 JUSB312_6_7 4.000 4.000 0 J 172 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
313 JUSB312_7_8 4.000 4.000 0 J 1 171 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
314 JUSB312_8_9 4.000 4.000 0 J 171 170 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
315 JUSB312_9_10 4.000 4.000 0 J 170 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
316 JUSB312_10_1 4.000 4.000 0 J 1 176 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
317 JUSB312_11_1 4.000 4.000 0 J 176 175 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
318 JUSB312_12_1 4.000 4.000 0 J 175 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
319 JUSB312_13_1 4.000 4.000 0 J 1 174 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
320 JUSB312_14_1 4.000 4.000 0 J 174 173 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
321 JUSB312_15_1 4.000 4.000 0 J 173 1 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
322 JUSB312_16_1 4.000 4.000 0 J 1 126 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
323 JUSB312_17_1 4.000 4.000 0 J 126 125 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
324 JUSB312_18_1 4.000 4.000 0 J 125 122 0 4.400 3.600 4.000 0.0000 99999 99999 4.4000 3.6000  
325 JUSB312_19_1/ 4.000 4.000 0 J 122 0 0 4.400 3.600 NA NA NA NA NA NA